1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun chosen: chosen { 9*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 init=/init kpti=0"; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun fiq-debugger { 13*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 14*4882a593Smuzhiyun rockchip,serial-id = <2>; 15*4882a593Smuzhiyun rockchip,wake-irq = <0>; 16*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 17*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 18*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 19*4882a593Smuzhiyun interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun pinctrl-0 = <&uart2m0_xfer>; 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun firmware { 26*4882a593Smuzhiyun firmware_android: android {}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun optee: optee { 29*4882a593Smuzhiyun compatible = "linaro,optee-tz"; 30*4882a593Smuzhiyun method = "smc"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun reserved-memory { 35*4882a593Smuzhiyun #address-cells = <2>; 36*4882a593Smuzhiyun #size-cells = <2>; 37*4882a593Smuzhiyun ranges; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 40*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 41*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun ramoops: ramoops@110000 { 45*4882a593Smuzhiyun compatible = "ramoops"; 46*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xf0000>; 47*4882a593Smuzhiyun record-size = <0x20000>; 48*4882a593Smuzhiyun console-size = <0x80000>; 49*4882a593Smuzhiyun ftrace-size = <0x00000>; 50*4882a593Smuzhiyun pmsg-size = <0x50000>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun vendor_storage_rm: vendor-storage-rm@00000000 { 54*4882a593Smuzhiyun compatible = "rockchip,vendor-storage-rm"; 55*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun vendor_storage: vendor-storage { 60*4882a593Smuzhiyun compatible = "rockchip,ram-vendor-storage"; 61*4882a593Smuzhiyun memory-region = <&vendor_storage_rm>; 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&cpu0_opp_table { 67*4882a593Smuzhiyun rockchip,avs = <1>; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&display_subsystem { 71*4882a593Smuzhiyun status = "disabled"; 72*4882a593Smuzhiyun logo-memory-region = <&drm_logo>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun route { 75*4882a593Smuzhiyun route_lvds: route-lvds { 76*4882a593Smuzhiyun status = "disabled"; 77*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 78*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 79*4882a593Smuzhiyun logo,mode = "center"; 80*4882a593Smuzhiyun charge_logo,mode = "center"; 81*4882a593Smuzhiyun connect = <&vopb_out_lvds>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun route_dsi: route-dsi { 85*4882a593Smuzhiyun status = "disabled"; 86*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 87*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 88*4882a593Smuzhiyun logo,mode = "center"; 89*4882a593Smuzhiyun charge_logo,mode = "center"; 90*4882a593Smuzhiyun connect = <&vopb_out_dsi>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun route_rgb: route-rgb { 94*4882a593Smuzhiyun status = "disabled"; 95*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 96*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 97*4882a593Smuzhiyun logo,mode = "center"; 98*4882a593Smuzhiyun charge_logo,mode = "center"; 99*4882a593Smuzhiyun connect = <&vopb_out_rgb>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&dsi { 105*4882a593Smuzhiyun panel@0 { 106*4882a593Smuzhiyun reg = <0>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun ports { 109*4882a593Smuzhiyun #address-cells = <1>; 110*4882a593Smuzhiyun #size-cells = <0>; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun port@0 { 113*4882a593Smuzhiyun reg = <0>; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun panel_in_dsi: endpoint { 116*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun ports { 123*4882a593Smuzhiyun #address-cells = <1>; 124*4882a593Smuzhiyun #size-cells = <0>; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun port@1 { 127*4882a593Smuzhiyun reg = <1>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun dsi_out_panel: endpoint { 130*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&rng { 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&video_phy { 141*4882a593Smuzhiyun status = "okay"; 142*4882a593Smuzhiyun}; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun&vopb { 145*4882a593Smuzhiyun support-multi-area; 146*4882a593Smuzhiyun}; 147