1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 compatible = "rockchip,linux", "rockchip,rk3358", "rockchip,px30"; 9 10 chosen { 11 bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait"; 12 }; 13 14 fiq-debugger { 15 compatible = "rockchip,fiq-debugger"; 16 rockchip,serial-id = <2>; 17 rockchip,wake-irq = <0>; 18 /* If enable uart uses irq instead of fiq */ 19 rockchip,irq-mode-enable = <0>; 20 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 21 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&uart2m0_xfer>; 24 status = "okay"; 25 }; 26 27 reserved-memory { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 drm_logo: drm-logo@00000000 { 33 compatible = "rockchip,drm-logo"; 34 reg = <0x0 0x0 0x0 0x0>; 35 }; 36 37 ramoops: ramoops@110000 { 38 compatible = "ramoops"; 39 reg = <0x0 0x110000 0x0 0xf0000>; 40 record-size = <0x20000>; 41 console-size = <0x80000>; 42 ftrace-size = <0x00000>; 43 pmsg-size = <0x50000>; 44 }; 45 }; 46}; 47 48&rng { 49 status = "okay"; 50}; 51 52&video_phy { 53 status = "okay"; 54}; 55