1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun compatible = "rockchip,linux", "rockchip,rk3326"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun aliases { 11*4882a593Smuzhiyun mmc0 = &emmc; 12*4882a593Smuzhiyun mmc1 = &sdmmc; 13*4882a593Smuzhiyun mmc2 = &sdio; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun fiq-debugger { 21*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 22*4882a593Smuzhiyun rockchip,serial-id = <2>; 23*4882a593Smuzhiyun rockchip,wake-irq = <0>; 24*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 25*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 26*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 27*4882a593Smuzhiyun interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 28*4882a593Smuzhiyun pinctrl-names = "default"; 29*4882a593Smuzhiyun pinctrl-0 = <&uart2m0_xfer>; 30*4882a593Smuzhiyun status = "okay"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reserved-memory { 34*4882a593Smuzhiyun #address-cells = <2>; 35*4882a593Smuzhiyun #size-cells = <2>; 36*4882a593Smuzhiyun ranges; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 39*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 40*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun ramoops: ramoops@110000 { 44*4882a593Smuzhiyun compatible = "ramoops"; 45*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xf0000>; 46*4882a593Smuzhiyun record-size = <0x20000>; 47*4882a593Smuzhiyun console-size = <0x80000>; 48*4882a593Smuzhiyun ftrace-size = <0x00000>; 49*4882a593Smuzhiyun pmsg-size = <0x50000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&cpu0_opp_table { 55*4882a593Smuzhiyun rockchip,avs = <1>; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&display_subsystem { 59*4882a593Smuzhiyun status = "disabled"; 60*4882a593Smuzhiyun logo-memory-region = <&drm_logo>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun route { 63*4882a593Smuzhiyun route_lvds: route-lvds { 64*4882a593Smuzhiyun status = "disabled"; 65*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 66*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 67*4882a593Smuzhiyun logo,mode = "center"; 68*4882a593Smuzhiyun charge_logo,mode = "center"; 69*4882a593Smuzhiyun connect = <&vopb_out_lvds>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun route_dsi: route-dsi { 73*4882a593Smuzhiyun status = "disabled"; 74*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 75*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 76*4882a593Smuzhiyun logo,mode = "center"; 77*4882a593Smuzhiyun charge_logo,mode = "center"; 78*4882a593Smuzhiyun connect = <&vopb_out_dsi>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun route_rgb: route-rgb { 82*4882a593Smuzhiyun status = "disabled"; 83*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 84*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 85*4882a593Smuzhiyun logo,mode = "center"; 86*4882a593Smuzhiyun charge_logo,mode = "center"; 87*4882a593Smuzhiyun connect = <&vopb_out_rgb>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&rng { 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&video_phy { 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99
