1 /*
2 * Copyright (c) 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <boot_rkimg.h>
8 #include <cli.h>
9 #include <debug_uart.h>
10 #include <miiphy.h>
11 #include <syscon.h>
12 #include <asm/arch/clock.h>
13 #include <asm/io.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/grf_rv1106.h>
16 #include <asm/arch/ioc_rv1106.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define PERI_GRF_BASE 0xff000000
21 #define PERI_GRF_PERI_CON1 0x0004
22
23 #define CORE_GRF_BASE 0xff040000
24 #define CORE_GRF_CACHE_PERI_ADDR_START 0x0024
25 #define CORE_GRF_CACHE_PERI_ADDR_END 0x0028
26 #define CORE_GRF_MCU_CACHE_MISC 0x002c
27
28 #define PERI_GRF_BASE 0xff000000
29 #define PERI_GRF_USBPHY_CON0 0x0050
30
31 #define PERI_SGRF_BASE 0xff070000
32 #define PERI_SGRF_FIREWALL_CON0 0x0020
33 #define PERI_SGRF_FIREWALL_CON1 0x0024
34 #define PERI_SGRF_FIREWALL_CON2 0x0028
35 #define PERI_SGRF_FIREWALL_CON3 0x002c
36 #define PERI_SGRF_FIREWALL_CON4 0x0030
37 #define PERI_SGRF_SOC_CON3 0x00bc
38
39 #define CORE_SGRF_BASE 0xff076000
40 #define CORE_SGRF_FIREWALL_CON0 0x0020
41 #define CORE_SGRF_FIREWALL_CON1 0x0024
42 #define CORE_SGRF_FIREWALL_CON2 0x0028
43 #define CORE_SGRF_FIREWALL_CON3 0x002c
44 #define CORE_SGRF_FIREWALL_CON4 0x0030
45 #define CORE_SGRF_CPU_CTRL_CON 0x0040
46 #define CORE_SGRF_HPMCU_BOOT_ADDR 0x0044
47
48 #define PMU_SGRF_BASE 0xff080000
49
50 /* QoS Generator Base Address */
51 #define QOS_CPU_BASE 0xff110000
52 #define QOS_CRYPTO_BASE 0xff120000
53 #define QOS_DECOM_BASE 0xff120080
54 #define QOS_DMAC_BASE 0xff120100
55 #define QOS_EMMC_BASE 0xff120180
56 #define QOS_FSPI_BASE 0xff120200
57 #define QOS_IVE_RD_BASE 0xff120280
58 #define QOS_IVE_WR_BASE 0xff120300
59 #define QOS_USB_BASE 0xff120380
60 #define QOS_ISP_BASE 0xff130000
61 #define QOS_SDMMC0_BASE 0xff130080
62 #define QOS_VICAP_BASE 0xff130100
63 #define QOS_NPU_BASE 0xff140000
64 #define QOS_VENC_BASE 0xff150000
65 #define QOS_VEPU_PP_BASE 0xff150080
66 #define QOS_MAC_BASE 0xff160000
67 #define QOS_RGA_RD_BASE 0xff160080
68 #define QOS_RGA_WR_BASE 0xff160100
69 #define QOS_SDIO_BASE 0xff160280
70 #define QOS_VOP_BASE 0xff160300
71
72 #define QOS_PRIORITY 0x0008
73 #define QOS_MODE 0x000c
74 #define QOS_BANDWIDTH 0x0010
75 #define QOS_SATURATION 0x0014
76 #define QOS_EXTCONTROL 0x0018
77
78 /* Shaping Base Address */
79 #define SHAPING_CPU_BASE 0xff110080
80 #define SHAPING_DECOM_BASE 0xff110400
81 #define SHAPING_IVE_RD_BASE 0xff120480
82 #define SHAPING_IVE_WR_BASE 0xff120500
83 #define SHAPING_ISP_BASE 0xff130180
84 #define SHAPING_VICAP_BASE 0xff130200
85 #define SHAPING_NPU_BASE 0xff140080
86 #define SHAPING_VENC_BASE 0xff150100
87 #define SHAPING_VEPU_PP_BASE 0xff150180
88 #define SHAPING_RGA_RD_BASE 0xff160380
89 #define SHAPING_RGA_WR_BASE 0xff160400
90 #define SHAPING_VOP_BASE 0xff160580
91
92 #define SHAPING_NBPKTMAX 0x0008
93
94 #define FW_DDR_BASE 0xff900000
95 #define FW_DDR_MST3_REG 0x4c
96 #define FW_SHRM_BASE 0xff910000
97 #define FW_SHRM_MST1_REG 0x44
98
99 #define PMU_BASE 0xff300000
100 #define PMU_BIU_IDLE_ST 0x00d8
101
102 #define CRU_BASE 0xff3b0000
103 #define CRU_GLB_RST_CON 0x0c10
104 #define CRU_PVTPLL0_CON0_L 0x1000
105 #define CRU_PVTPLL0_CON1_L 0x1008
106 #define CRU_PVTPLL1_CON0_L 0x1030
107 #define CRU_PVTPLL1_CON1_L 0x1038
108
109 #define CORECRU_BASE 0xff3b8000
110 #define CORECRU_CORESOFTRST_CON01 0xa04
111
112 #define USBPHY_APB_BASE 0xff3e0000
113 #define USBPHY_FSLS_DIFF_RECEIVER 0x0100
114
115 #define GPIO0_IOC_BASE 0xFF388000
116 #define GPIO1_IOC_BASE 0xFF538000
117 #define GPIO2_IOC_BASE 0xFF548000
118 #define GPIO3_IOC_BASE 0xFF558000
119 #define GPIO4_IOC_BASE 0xFF568000
120
121 #define GPIO3A_IOMUX_SEL_L 0x0040
122 #define GPIO3A_IOMUX_SEL_H 0x0044
123
124 #define GPIO4A_IOMUX_SEL_L 0x000
125 #define GPIO4A_IOMUX_SEL_H 0x004
126 #define GPIO4B_IOMUX_SEL_L 0x008
127
128 #define GPIO4_IOC_GPIO4B_DS0 0x0030
129
130 /* OS_REG1[2:0]: chip ver */
131 #define CHIP_VER_REG 0xff020204
132 #define CHIP_VER_MSK 0x7
133 #define V(x) ((x) - 1)
134 #define ROM_VER_REG 0xffff4ffc
135 #define ROM_V2 0x30303256
136
137 /* uart0 iomux */
138 /* gpio0a0 */
139 #define UART0_RX_M0 1
140 #define UART0_RX_M0_OFFSET 0
141 #define UART0_RX_M0_ADDR (GPIO1_IOC_BASE)
142 /* gpio0a1 */
143 #define UART0_TX_M0 1
144 #define UART0_TX_M0_OFFSET 4
145 #define UART0_TX_M0_ADDR (GPIO1_IOC_BASE)
146
147 /* gpio2b0 */
148 #define UART0_RX_M1 1
149 #define UART0_RX_M1_OFFSET 0
150 #define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x28)
151 /* gpio2b1 */
152 #define UART0_TX_M1 1
153 #define UART0_TX_M1_OFFSET 4
154 #define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x28)
155
156 /* gpio4a0 */
157 #define UART0_RX_M2 3
158 #define UART0_RX_M2_OFFSET 0
159 #define UART0_RX_M2_ADDR (GPIO4_IOC_BASE)
160 /* gpio4a1 */
161 #define UART0_TX_M2 3
162 #define UART0_TX_M2_OFFSET 4
163 #define UART0_TX_M2_ADDR (GPIO4_IOC_BASE)
164
165 /* uart1 iomux */
166 /* gpio1a4 */
167 #define UART1_RX_M0 1
168 #define UART1_RX_M0_OFFSET 0
169 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x4)
170 /* gpio1a3 */
171 #define UART1_TX_M0 1
172 #define UART1_TX_M0_OFFSET 12
173 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE)
174
175 /* gpio2a5 */
176 #define UART1_RX_M1 4
177 #define UART1_RX_M1_OFFSET 4
178 #define UART1_RX_M1_ADDR (GPIO2_IOC_BASE + 0x24)
179 /* gpio2a4 */
180 #define UART1_TX_M1 4
181 #define UART1_TX_M1_OFFSET 0
182 #define UART1_TX_M1_ADDR (GPIO2_IOC_BASE + 0x24)
183
184 /* gpio4a7 */
185 #define UART1_RX_M2 3
186 #define UART1_RX_M2_OFFSET 12
187 #define UART1_RX_M2_ADDR (GPIO4_IOC_BASE + 0x4)
188 /* gpio4a5 */
189 #define UART1_TX_M2 3
190 #define UART1_TX_M2_OFFSET 4
191 #define UART1_TX_M2_ADDR (GPIO4_IOC_BASE + 0x4)
192
193 /* uart2 iomux */
194 /* gpio3a3 */
195 #define UART2_RX_M0 2
196 #define UART2_RX_M0_OFFSET 12
197 #define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x40)
198 /* gpio3a2 */
199 #define UART2_TX_M0 2
200 #define UART2_TX_M0_OFFSET 8
201 #define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x40)
202
203 /* gpio1b3 */
204 #define UART2_RX_M1 2
205 #define UART2_RX_M1_OFFSET 12
206 #define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x8)
207 /* gpio1b2 */
208 #define UART2_TX_M1 2
209 #define UART2_TX_M1_OFFSET 8
210 #define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x8)
211
212 /* uart3 iomux */
213 /* gpio1a1 */
214 #define UART3_RX_M0 1
215 #define UART3_RX_M0_OFFSET 4
216 #define UART3_RX_M0_ADDR (GPIO1_IOC_BASE)
217 /* gpio1a0 */
218 #define UART3_TX_M0 1
219 #define UART3_TX_M0_OFFSET 0
220 #define UART3_TX_M0_ADDR (GPIO1_IOC_BASE)
221
222 /* gpio1d1 */
223 #define UART3_RX_M1 5
224 #define UART3_RX_M1_OFFSET 4
225 #define UART3_RX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
226 /* gpio1d0 */
227 #define UART3_TX_M1 5
228 #define UART3_TX_M1_OFFSET 0
229 #define UART3_TX_M1_ADDR (GPIO2_IOC_BASE + 0x18)
230
231 /* uart4 iomux */
232 /* gpio1b0 */
233 #define UART4_RX_M0 1
234 #define UART4_RX_M0_OFFSET 0
235 #define UART4_RX_M0_ADDR (GPIO1_IOC_BASE + 0x8)
236 /* gpio1b1 */
237 #define UART4_TX_M0 1
238 #define UART4_TX_M0_OFFSET 4
239 #define UART4_TX_M0_ADDR (GPIO1_IOC_BASE + 0x8)
240
241 /* gpio1c4 */
242 #define UART4_RX_M1 4
243 #define UART4_RX_M1_OFFSET 0
244 #define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x14)
245 /* gpio1c5 */
246 #define UART4_TX_M1 4
247 #define UART4_TX_M1_OFFSET 4
248 #define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x14)
249
250 /* uart5 iomux */
251 /* gpio3a7 */
252 #define UART5_RX_M0 2
253 #define UART5_RX_M0_OFFSET 11
254 #define UART5_RX_M0_ADDR (GPIO3_IOC_BASE + 0x44)
255 /* gpio3a6 */
256 #define UART5_TX_M0 1
257 #define UART5_TX_M0_OFFSET 8
258 #define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x44)
259
260 /* gpio1d2 */
261 #define UART5_RX_M1 4
262 #define UART5_RX_M1_OFFSET 8
263 #define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
264 /* gpio1d3 */
265 #define UART5_TX_M1 4
266 #define UART5_TX_M1_OFFSET 12
267 #define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
268
269 /* gpio3d0 */
270 #define UART5_RX_M2 2
271 #define UART5_RX_M2_OFFSET 0
272 #define UART5_RX_M2_ADDR (GPIO3_IOC_BASE + 0x58)
273 /* gpio3c7 */
274 #define UART5_TX_M2 2
275 #define UART5_TX_M2_OFFSET 12
276 #define UART5_TX_M2_ADDR (GPIO4_IOC_BASE + 0x54)
277
278 #define set_uart_iomux(bits_offset, bits_val, addr) \
279 writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
280
281 #define set_uart_iomux_rx(ID, MODE) \
282 set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
283 #define set_uart_iomux_tx(ID, MODE) \
284 set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
285
board_debug_uart_init(void)286 void board_debug_uart_init(void)
287 {
288 /* UART 0 */
289 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4a0000)
290
291 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
292 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
293
294 /* UART0_M0 Switch iomux */
295 set_uart_iomux_rx(0, 0);
296 set_uart_iomux_tx(0, 0);
297 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
298 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
299
300 /* UART0_M1 Switch iomux */
301 set_uart_iomux_rx(0, 1);
302 set_uart_iomux_tx(0, 1);
303 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
304 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
305
306 /* UART0_M2 Switch iomux */
307 set_uart_iomux_rx(0, 2);
308 set_uart_iomux_tx(0, 2);
309 #endif
310
311 /* UART 1 */
312 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4b0000)
313
314 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
315 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
316
317 /* UART1_M0 Switch iomux */
318 set_uart_iomux_rx(1, 0);
319 set_uart_iomux_tx(1, 0);
320 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
321 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
322
323 /* UART1_M1 Switch iomux */
324 set_uart_iomux_rx(1, 1);
325 set_uart_iomux_tx(1, 1);
326 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
327 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
328
329 /* UART1_M2 Switch iomux */
330 set_uart_iomux_rx(1, 2);
331 set_uart_iomux_tx(1, 2);
332 #endif
333 /* UART 2 */
334 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4c0000)
335
336 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
337 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
338
339 /* UART2_M0 Switch iomux */
340 set_uart_iomux_rx(2, 0);
341 set_uart_iomux_tx(2, 0);
342 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
343 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
344
345 /* UART2_M1 Switch iomux */
346 set_uart_iomux_rx(2, 1);
347 set_uart_iomux_tx(2, 1);
348 #endif
349
350 /* UART 3 */
351 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4d0000)
352 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
353 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
354
355 /* UART3_M0 Switch iomux */
356 set_uart_iomux_rx(3, 0);
357 set_uart_iomux_tx(3, 0);
358 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
359 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
360
361 /* UART3_M1 Switch iomux */
362 set_uart_iomux_rx(3, 1);
363 set_uart_iomux_tx(3, 1);
364 #endif
365 /* UART 4 */
366 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4e0000)
367 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
368 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
369
370 /* UART4_M0 Switch iomux */
371 set_uart_iomux_rx(4, 0);
372 set_uart_iomux_tx(4, 0);
373 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
374 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
375
376 /* UART4_M1 Switch iomux */
377 set_uart_iomux_rx(4, 1);
378 set_uart_iomux_tx(4, 1);
379 #endif
380 /* UART 5 */
381 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4f0000)
382 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
383 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
384
385 /* UART5_M0 Switch iomux */
386 set_uart_iomux_rx(5, 0);
387 set_uart_iomux_tx(5, 0);
388 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
389 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
390
391 /* UART5_M1 Switch iomux */
392 set_uart_iomux_rx(5, 1);
393 set_uart_iomux_tx(5, 1);
394 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
395 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
396
397 /* UART5_M2 Switch iomux */
398 set_uart_iomux_rx(5, 2);
399 set_uart_iomux_tx(5, 2);
400 #endif
401 #endif
402 }
403
arch_cpu_init(void)404 int arch_cpu_init(void)
405 {
406 #ifdef CONFIG_SPL_BUILD
407 /* Save chip version to OS_REG1[2:0] */
408 if (readl(ROM_VER_REG) == ROM_V2)
409 writel((readl(CHIP_VER_REG) & ~CHIP_VER_MSK) | V(2), CHIP_VER_REG);
410 else
411 writel((readl(CHIP_VER_REG) & ~CHIP_VER_MSK) | V(1), CHIP_VER_REG);
412
413 /* Set all devices to Non-secure */
414 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON0);
415 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON1);
416 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON2);
417 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON3);
418 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON4);
419 writel(0x000f0000, PERI_SGRF_BASE + PERI_SGRF_SOC_CON3);
420 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON0);
421 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON1);
422 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON2);
423 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON3);
424 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON4);
425 writel(0x00030002, CORE_SGRF_BASE + CORE_SGRF_CPU_CTRL_CON);
426 writel(0x20000000, PMU_SGRF_BASE);
427
428 /* Set the emmc and fspi to access secure area */
429 writel(0x00000000, FW_DDR_BASE + FW_DDR_MST3_REG);
430 writel(0xff00ffff, FW_SHRM_BASE + FW_SHRM_MST1_REG);
431
432 /* Set fspi clk 6mA */
433 if ((readl(GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L) & 0x70) == 0x20)
434 writel(0x3f000700, GPIO4_IOC_BASE + GPIO4_IOC_GPIO4B_DS0);
435
436 /*
437 * Set the USB2 PHY in suspend mode and turn off the
438 * USB2 PHY FS/LS differential receiver to save power:
439 * VCC1V8_USB : reduce 3.8 mA
440 * VDD_0V9 : reduce 4.4 mA
441 */
442 writel(0x01ff01d1, PERI_GRF_BASE + PERI_GRF_USBPHY_CON0);
443 writel(0x00000000, USBPHY_APB_BASE + USBPHY_FSLS_DIFF_RECEIVER);
444
445 /* release the wdt */
446 writel(0x2000200, PERI_GRF_BASE + PERI_GRF_PERI_CON1);
447 writel(0x400040, CRU_BASE + CRU_GLB_RST_CON);
448
449 /*
450 * When venc/npu use pvtpll, reboot will fail, because
451 * pvtpll is reset before venc/npu reset, so venc/npu
452 * is not completely reset, system will block when access
453 * NoC in SPL.
454 * Enable pvtpll can make venc/npu reset go on, wait
455 * until venc/npu is reset completely.
456 */
457 writel(0xffff0018, CRU_BASE + CRU_PVTPLL0_CON1_L);
458 writel(0x00030003, CRU_BASE + CRU_PVTPLL0_CON0_L);
459 writel(0xffff0018, CRU_BASE + CRU_PVTPLL1_CON1_L);
460 writel(0x00030003, CRU_BASE + CRU_PVTPLL1_CON0_L);
461 udelay(2);
462
463 if (readl(PMU_BASE + PMU_BIU_IDLE_ST)) {
464 printascii("BAD PMU_BIU_IDLE_ST: ");
465 printhex8(readl(PMU_BASE + PMU_BIU_IDLE_ST));
466 }
467
468 /*
469 * Limits npu max transport packets to 4 for route to scheduler,
470 * give much more chance for other controllers to access memory.
471 * such as VENC.
472 */
473 writel(0x4, SHAPING_NPU_BASE + SHAPING_NBPKTMAX);
474
475 /* Improve VENC QOS PRIORITY */
476 writel(0x303, QOS_VENC_BASE + QOS_PRIORITY);
477
478 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY
479 /* Pinctrl is disabled, set sdmmc0 iomux here */
480 writel(0xfff01110, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L);
481 writel(0xffff1111, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H);
482 #endif
483
484 #if defined(CONFIG_ROCKCHIP_SFC_IOMUX)
485 /* fspi iomux */
486 writel(0x0f000700, GPIO4_IOC_BASE + 0x0030);
487 writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
488 writel(0x0f0f0202, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
489 writel(0x00ff0022, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
490 #elif defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
491 /* emmc iomux */
492 writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
493 writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
494 writel(0x00ff0011, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
495 #endif
496
497 #endif
498 return 0;
499 }
500
501 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)502 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
503 {
504 /* set the mcu uncache area, usually set the devices address */
505 writel(0xff000, CORE_GRF_BASE + CORE_GRF_CACHE_PERI_ADDR_START);
506 writel(0xffc00, CORE_GRF_BASE + CORE_GRF_CACHE_PERI_ADDR_END);
507 /* Reset the hp mcu */
508 writel(0x1e001e, CORECRU_BASE + CORECRU_CORESOFTRST_CON01);
509 /* set the mcu addr */
510 writel(entry_point, CORE_SGRF_BASE + CORE_SGRF_HPMCU_BOOT_ADDR);
511 /* release the mcu */
512 writel(0x1e0000, CORECRU_BASE + CORECRU_CORESOFTRST_CON01);
513
514 return 0;
515 }
516
rk_meta_process(void)517 void rk_meta_process(void)
518 {
519 writel(0x00080008, CORE_GRF_BASE + CORE_GRF_MCU_CACHE_MISC);
520 }
521 #endif
522
523 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY
rk_board_scan_bootdev(void)524 int rk_board_scan_bootdev(void)
525 {
526 char *devtype, *devnum;
527
528 if (!run_command("blk dev mmc 1", 0) &&
529 !run_command("rkimgtest mmc 1", 0)) {
530 devtype = "mmc";
531 devnum = "1";
532 } else {
533 run_command("blk dev mtd 2", 0);
534 devtype = "mtd";
535 devnum = "2";
536 }
537 env_set("devtype", devtype);
538 env_set("devnum", devnum);
539
540 return 0;
541 }
542 #endif
543
544 #if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
545 #define GMAC_NODE_FDT_PATH "/ethernet@ffa80000"
546 #define RK630_MII_NAME "ethernet@ffa80000"
547 #define PHY_ADDR 2
548 #define PAGE_SWITCH 0x1f
549 #define DISABLE_APS_REG 0x12
550 #define DISABLE_APS_VAL 0x4824
551 #define PHYAFE_PDCW_REG 0x1c
552 #define PHYAFE_PDCW_VAL 0x8880
553 #define PD_ANALOG_REG 0x0
554 #define PD_ANALOG_VAL 0x3900
555 #define RV1106_MACPHY_SHUTDOWN BIT(1)
556 #define RV1106_MACPHY_ENABLE_MASK BIT(1)
557
rk_board_fdt_pwrdn_gmac(const void * blob)558 static int rk_board_fdt_pwrdn_gmac(const void *blob)
559 {
560 void *fdt = (void *)gd->fdt_blob;
561 struct rv1106_grf *grf;
562 int gmac_node;
563
564 /* Turn off GMAC FEPHY to reduce chip power consumption at uboot level,
565 * if the gmac node is disabled at kernel dtb. RV1106/1103 has the
566 * internal gmac phy, u-boot.dtb defines and enables the gmac node
567 * by default, so even if the gmac node of the kernel dts is disabled,
568 * U-Boot will enable and initialize the gmac phy. So it is not okay
569 * to turn off gmac phy by default in arch_cpu_init(), need to turn off
570 * gmac phy in the current function.
571 */
572 gmac_node = fdt_path_offset(gd->fdt_blob, GMAC_NODE_FDT_PATH);
573 if (fdt_stringlist_search(fdt, gmac_node, "status", "disabled") >= 0) {
574 /* switch to page 1 */
575 miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0100);
576 miiphy_write(RK630_MII_NAME, PHY_ADDR, DISABLE_APS_REG,
577 DISABLE_APS_VAL);
578 /* switch to pae 6 */
579 miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0600);
580 miiphy_write(RK630_MII_NAME, PHY_ADDR, PHYAFE_PDCW_REG,
581 PHYAFE_PDCW_VAL);
582 /* switch to page 0 */
583 miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0000);
584 miiphy_write(RK630_MII_NAME, PHY_ADDR, PD_ANALOG_REG,
585 PD_ANALOG_VAL);
586
587 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
588 if (grf)
589 rk_clrsetreg(&grf->macphy_con0,
590 RV1106_MACPHY_ENABLE_MASK,
591 RV1106_MACPHY_SHUTDOWN);
592 }
593
594 return 0;
595 }
596 #endif
597
rk_board_fdt_fixup(const void * blob)598 int rk_board_fdt_fixup(const void *blob)
599 {
600 #if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
601 rk_board_fdt_pwrdn_gmac(blob);
602 #endif
603
604 return 0;
605 }
606