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/OK3568_Linux_fs/u-boot/include/
H A Dpcmcia.h42 # define _slot_ 0
70 /* Window 0:
71 * Base: 0xFE100000 CS1
77 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
86 * Base: 0xFE100080 CS1
92 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
101 * Base: 0xFE100100 CS2
107 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
118 #define CONFIG_SYS_PCMCIA_PBR3 0
119 #define CONFIG_SYS_PCMCIA_POR3 0
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dtb100.h17 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
22 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
26 #define CONFIG_SYS_LOAD_ADDR 0x82000000
49 #define ETH0_BASE_ADDRESS 0xFE100000
50 #define ETH1_BASE_ADDRESS 0xFE110000
63 #define CONFIG_ENV_OFFSET 0
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Drcar-pci-ep.yaml72 reg = <0xfe000000 0x80000>,
73 <0xfe100000 0x100000>,
74 <0xfe200000 0x200000>,
75 <0x30000000 0x8000000>,
76 <0x38000000 0x8000000>;
H A Drcar-pci.txt55 reg = <0 0xfe000000 0 0x80000>;
58 bus-range = <0x00 0xff>;
60 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
61 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
62 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
63 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
64 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
65 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
66 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
68 interrupt-map-mask = <0 0 0 0>;
[all …]
/OK3568_Linux_fs/kernel/arch/sh/drivers/pci/
H A Dpcie-sh7786.c45 .name = "PCIe0 MEM 0",
46 .start = 0xfd000000,
47 .end = 0xfd000000 + SZ_8M - 1,
51 .start = 0xc0000000,
52 .end = 0xc0000000 + SZ_512M - 1,
56 .start = 0x10000000,
57 .end = 0x10000000 + SZ_64M - 1,
61 .start = 0xfe100000,
62 .end = 0xfe100000 + SZ_1M - 1,
69 .name = "PCIe1 MEM 0",
[all …]
/OK3568_Linux_fs/kernel/arch/arc/boot/dts/
H A Dabilis_tb10x.dtsi18 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 ranges = <0xfe000000 0xfe000000 0x02000000
45 0x000f0000 0x000f0000 0x00010000>;
50 #clock-cells = <0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
69 reg = <0xff10601c 0x4>;
79 reg = <0xfe002000 0x20>;
[all …]
/OK3568_Linux_fs/kernel/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7750.c19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
26 .start = evt2irq(0x480),
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 .id = 0,
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
82 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/lg/
H A Dlg1312.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
57 cpu_suspend = <0x84000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0x84000003>;
66 reg = <0x0 0xc0001000 0x1000>,
[all …]
H A Dlg1313.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
57 cpu_suspend = <0x84000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0x84000003>;
66 reg = <0x0 0xc0001000 0x1000>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/
H A Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a774a1.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
106 #size-cells = <0>;
[all …]
H A Dr8a774b1.dtsi21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
74 #size-cells = <0>;
[all …]
H A Dr8a774e1.dtsi21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
95 #size-cells = <0>;
[all …]
H A Dr8a77980.dtsi31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #size-cells = <0>;
39 a53_0: cpu@0 {
42 reg = <0>;
89 #clock-cells = <0>;
91 clock-frequency = <0>;
96 #clock-cells = <0>;
98 clock-frequency = <0>;
104 #clock-cells = <0>;
[all …]
H A Dr8a77990.dtsi29 * The external audio clocks are configured as 0 Hz fixed frequency
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
81 #size-cells = <0>;
[all …]
H A Dr8a77961.dtsi20 * The external audio clocks are configured as 0 Hz fixed frequency
26 #clock-cells = <0>;
27 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
118 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/drivers/pci/
H A Dpci_tegra.c48 #define AFI_AXI_BAR0_SZ 0x00
49 #define AFI_AXI_BAR1_SZ 0x04
50 #define AFI_AXI_BAR2_SZ 0x08
51 #define AFI_AXI_BAR3_SZ 0x0c
52 #define AFI_AXI_BAR4_SZ 0x10
53 #define AFI_AXI_BAR5_SZ 0x14
55 #define AFI_AXI_BAR0_START 0x18
56 #define AFI_AXI_BAR1_START 0x1c
57 #define AFI_AXI_BAR2_START 0x20
58 #define AFI_AXI_BAR3_START 0x24
[all …]
/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig.debug138 0x80000000 | 0xf0000000 | UART0
139 0x80004000 | 0xf0004000 | UART1
140 0x80008000 | 0xf0008000 | UART2
141 0x8000c000 | 0xf000c000 | UART3
142 0x80010000 | 0xf0010000 | UART4
143 0x80014000 | 0xf0014000 | UART5
144 0x80018000 | 0xf0018000 | UART6
145 0x8001c000 | 0xf001c000 | UART7
146 0x80020000 | 0xf0020000 | UART8
147 0x80024000 | 0xf0024000 | UART9
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dr8a7795.dtsi38 #size-cells = <0>;
40 a57_0: cpu@0 {
42 reg = <0x0>;
51 reg = <0x1>;
60 reg = <0x2>;
69 reg = <0x3>;
78 reg = <0x100>;
87 reg = <0x101>;
96 reg = <0x102>;
105 reg = <0x103>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpci-tegra.c51 #define AFI_AXI_BAR0_SZ 0x00
52 #define AFI_AXI_BAR1_SZ 0x04
53 #define AFI_AXI_BAR2_SZ 0x08
54 #define AFI_AXI_BAR3_SZ 0x0c
55 #define AFI_AXI_BAR4_SZ 0x10
56 #define AFI_AXI_BAR5_SZ 0x14
58 #define AFI_AXI_BAR0_START 0x18
59 #define AFI_AXI_BAR1_START 0x1c
60 #define AFI_AXI_BAR2_START 0x20
61 #define AFI_AXI_BAR3_START 0x24
[all …]

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