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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x000FFFFF
16 #define GPU_2D_ARB_BASE_ADDR 0x02200000
17 #define GPU_2D_ARB_END_ADDR 0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR 0x02204000
19 #define OPENVG_ARB_END_ADDR 0x02207FFF
21 #define CAAM_ARB_BASE_ADDR 0x00100000
22 #define CAAM_ARB_END_ADDR 0x00107FFF
23 #define GPU_ARB_BASE_ADDR 0x01800000
24 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,glink.txt67 reg = <0x9820000 0x1000>;
74 reg = <0x68000 0x6000>;
84 mboxes = <&apcs_glb 0>;
90 qcom,intents = <0x400 5
91 0x800 1>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml66 const: 0
69 "^dai-link@[0-9a-f]$":
187 reg = <0 0x62d87000 0 0x68000>,
188 <0 0x62f00000 0 0x29000>;
191 iommus = <&apps_smmu 0x1020 0>,
192 <&apps_smmu 0x1032 0>;
193 power-domains = <&lpass_hm 0>;
206 interrupts = <0 160 1>,
207 <0 268 1>;
213 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ux500/
H A Ddb8500-regs.h10 #define U8500_ESRAM_BASE 0x40000000
11 #define U8500_ESRAM_BANK_SIZE 0x00020000
21 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
28 #define U8500_PER3_BASE 0x80000000
29 #define U8500_STM_BASE 0x80100000
30 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
31 #define U8500_PER2_BASE 0x80110000
32 #define U8500_PER1_BASE 0x80120000
33 #define U8500_B2R2_BASE 0x80130000
34 #define U8500_HSEM_BASE 0x80140000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/cfg/
H A D8000.c77 #define IWL8000_NVM_VERSION 0x0a1d
80 #define IWL8260_DCCM_OFFSET 0x800000
81 #define IWL8260_DCCM_LEN 0x18000
82 #define IWL8260_DCCM2_OFFSET 0x880000
83 #define IWL8260_DCCM2_LEN 0x8000
84 #define IWL8260_SMEM_OFFSET 0x400000
85 #define IWL8260_SMEM_LEN 0x68000
154 .min_umac_error_event_table = 0x800000
H A D9000.c67 #define IWL9000_NVM_VERSION 0x0a1d
70 #define IWL9000_DCCM_OFFSET 0x800000
71 #define IWL9000_DCCM_LEN 0x18000
72 #define IWL9000_DCCM2_OFFSET 0x880000
73 #define IWL9000_DCCM2_LEN 0x8000
74 #define IWL9000_SMEM_OFFSET 0x400000
75 #define IWL9000_SMEM_LEN 0x68000
143 .min_umac_error_event_table = 0x800000, \
144 .d3_debug_data_base_addr = 0x401000, \
162 .mask = 0xffffffff, \
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_regs.h22 #define mmMME0_QM_GLBL_CFG0 0x68000
24 #define mmMME0_QM_GLBL_CFG1 0x68004
26 #define mmMME0_QM_GLBL_PROT 0x68008
28 #define mmMME0_QM_GLBL_ERR_CFG 0x6800C
30 #define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
32 #define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
34 #define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
36 #define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
38 #define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020
40 #define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/hdcp/
H A Dhdcp_msg.c79 [HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
80 [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
81 [HDCP_MESSAGE_ID_READ_PJ] = 0xA,
82 [HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
83 [HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
84 [HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
85 [HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
86 [HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
87 [HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
88 [HDCP_MESSAGE_ID_READ_VH_2] = 0x28,
[all …]
/OK3568_Linux_fs/kernel/drivers/parisc/
H A Dsuperio.c32 * Function 0 is an IDE controller. It is identical to a PC87415 IDE
54 * 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
55 * 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
100 outb (OCW3_POLL,IC_PIC1+0); in superio_interrupt()
102 results = inb(IC_PIC1+0); in superio_interrupt()
105 * Bit 7: 1 = active Interrupt; 0 = no Interrupt pending in superio_interrupt()
107 * Bits 2-0: highest priority, active requesting interrupt ID (0-7) in superio_interrupt()
109 if ((results & 0x80) == 0) { in superio_interrupt()
118 local_irq = results & 0x0f; in superio_interrupt()
129 outb(OCW3_ISR,IC_PIC1+0); in superio_interrupt()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp_ddc.c29 #define HDCP_I2C_ADDR 0x3a /* 0x74 >> 1*/
30 #define KSV_READ_SIZE 0xf /* 0x6803b - 0x6802c */
40 MOD_HDCP_MESSAGE_ID_READ_BKSV = 0,
81 [MOD_HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
82 [MOD_HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
83 [MOD_HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
84 [MOD_HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
85 [MOD_HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
86 [MOD_HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
87 [MOD_HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_0_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_9_1_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_9_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_1_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_9_4_1_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
/OK3568_Linux_fs/u-boot/include/drm/
H A Ddrm_dp_helper.h45 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
47 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
51 #define DP_MSA_MISC_6_BPC (0 << 5)
67 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
68 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
70 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
71 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
72 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1106.dtsi55 #size-cells = <0>;
60 reg = <0xf00>;
106 rockchip,wake-irq = <0>;
107 rockchip,irq-mode-enable = <0>;
133 size = <0x800000>;
211 thermal-sensors = <&tsadc 0>;
213 threshold: trip-point-0 {
244 #clock-cells = <0>;
249 reg = <0xff000000 0x68000>;
258 offset = <0x20200>;
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c18 {0x800, 0x810},
19 {0x820, 0x82C},
20 {0x830, 0x8F4},
21 {0x90C, 0x91C},
22 {0xA14, 0xA18},
23 {0xA84, 0xA94},
24 {0xAA8, 0xAD4},
25 {0xADC, 0xB40},
26 {0x1000, 0x10A4},
27 {0x10BC, 0x111C},
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1106.dtsi72 #clock-cells = <0>;
76 rkvenc_pvtpll: pvtpll-0 {
80 #clock-cells = <0>;
87 #clock-cells = <0>;
94 #clock-cells = <0>;
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0x0>;
118 rockchip,pvtpll-avg-offset = <0x4001c>;
227 rockchip,wake-irq = <0>;
[all …]
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
10 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
11 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
12 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
13 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
14 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
[all …]
/OK3568_Linux_fs/kernel/include/drm/
H A Ddrm_dp_helper.h49 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
51 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
55 #define DP_MSA_MISC_6_BPC (0 << 5)
71 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
72 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
73 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
74 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
75 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
76 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
77 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgcc-msm8916.c46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
H A Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]

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