Lines Matching +full:0 +full:x68000
45 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
47 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
51 #define DP_MSA_MISC_6_BPC (0 << 5)
67 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
68 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
70 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
71 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
72 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
74 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
75 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
76 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
77 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
78 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
79 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
80 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
81 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
82 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
83 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
88 #define DP_AUX_I2C_WRITE 0x0
89 #define DP_AUX_I2C_READ 0x1
90 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
91 #define DP_AUX_I2C_MOT 0x4
92 #define DP_AUX_NATIVE_WRITE 0x8
93 #define DP_AUX_NATIVE_READ 0x9
95 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
96 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
97 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
98 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
100 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
101 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
102 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
103 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
107 #define DP_DPCD_REV 0x000
108 # define DP_DPCD_REV_10 0x10
109 # define DP_DPCD_REV_11 0x11
110 # define DP_DPCD_REV_12 0x12
111 # define DP_DPCD_REV_13 0x13
112 # define DP_DPCD_REV_14 0x14
114 #define DP_MAX_LINK_RATE 0x001
116 #define DP_MAX_LANE_COUNT 0x002
117 # define DP_MAX_LANE_COUNT_MASK 0x1f
121 #define DP_MAX_DOWNSPREAD 0x003
122 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
126 #define DP_NORP 0x004
128 #define DP_DOWNSTREAMPORT_PRESENT 0x005
129 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
130 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
131 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
138 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
139 # define DP_CAP_ANSI_8B10B (1 << 0)
141 #define DP_DOWN_STREAM_PORT_COUNT 0x007
142 # define DP_PORT_COUNT_MASK 0x0f
146 #define DP_RECEIVE_PORT_0_CAP_0 0x008
150 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
152 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
153 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
155 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
156 # define DP_I2C_SPEED_1K 0x01
157 # define DP_I2C_SPEED_5K 0x02
158 # define DP_I2C_SPEED_10K 0x04
159 # define DP_I2C_SPEED_100K 0x08
160 # define DP_I2C_SPEED_400K 0x10
161 # define DP_I2C_SPEED_1M 0x20
163 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
164 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
168 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
169 # define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
172 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
173 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
176 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
180 #define DP_FAUX_CAP 0x020 /* 1.2 */
181 # define DP_FAUX_CAP_1 (1 << 0)
183 #define DP_MSTM_CAP 0x021 /* 1.2 */
184 # define DP_MST_CAP (1 << 0)
186 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
189 #define DP_AV_GRANULARITY 0x023
190 # define DP_AG_FACTOR_MASK (0xf << 0)
191 # define DP_AG_FACTOR_3MS (0 << 0)
192 # define DP_AG_FACTOR_2MS (1 << 0)
193 # define DP_AG_FACTOR_1MS (2 << 0)
194 # define DP_AG_FACTOR_500US (3 << 0)
195 # define DP_AG_FACTOR_200US (4 << 0)
196 # define DP_AG_FACTOR_100US (5 << 0)
197 # define DP_AG_FACTOR_10US (6 << 0)
198 # define DP_AG_FACTOR_1US (7 << 0)
199 # define DP_VG_FACTOR_MASK (0xf << 4)
200 # define DP_VG_FACTOR_3MS (0 << 4)
207 #define DP_AUD_DEC_LAT0 0x024
208 #define DP_AUD_DEC_LAT1 0x025
210 #define DP_AUD_PP_LAT0 0x026
211 #define DP_AUD_PP_LAT1 0x027
213 #define DP_VID_INTER_LAT 0x028
215 #define DP_VID_PROG_LAT 0x029
217 #define DP_REP_LAT 0x02a
219 #define DP_AUD_DEL_INS0 0x02b
220 #define DP_AUD_DEL_INS1 0x02c
221 #define DP_AUD_DEL_INS2 0x02d
224 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
225 # define DP_ALPM_CAP (1 << 0)
227 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
228 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
230 #define DP_GUID 0x030 /* 1.2 */
232 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
233 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
235 #define DP_DSC_REV 0x061
236 # define DP_DSC_MAJOR_MASK (0xf << 0)
237 # define DP_DSC_MINOR_MASK (0xf << 4)
238 # define DP_DSC_MAJOR_SHIFT 0
241 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
242 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
243 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
244 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
245 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
247 #define DP_DSC_RC_BUF_SIZE 0x063
249 #define DP_DSC_SLICE_CAP_1 0x064
250 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
258 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
259 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
260 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
261 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
262 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
263 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
264 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
265 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
266 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
267 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
268 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
270 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
271 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
273 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
275 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
277 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
278 # define DP_DSC_RGB (1 << 0)
284 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
289 #define DP_DSC_PEAK_THROUGHPUT 0x06B
290 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
291 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
292 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
293 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
294 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
295 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
296 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
297 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
298 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
299 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
300 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
301 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
302 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
303 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
304 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
305 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
306 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
323 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
325 #define DP_DSC_SLICE_CAP_2 0x06D
326 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
330 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
331 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
332 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
333 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
334 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
335 # define DP_DSC_BITS_PER_PIXEL_1 0x4
337 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
342 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
344 # define DP_PSR_SETUP_TIME_330 (0 << 1)
356 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
363 /* offset 0 */
364 #define DP_DOWNSTREAM_PORT_0 0x80
365 # define DP_DS_PORT_TYPE_MASK (7 << 0)
366 # define DP_DS_PORT_TYPE_DP 0
376 # define DP_DS_MAX_BPC_MASK (3 << 0)
377 # define DP_DS_8BPC 0
383 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
384 # define DP_FEC_CAPABLE (1 << 0)
390 #define DP_LINK_BW_SET 0x100
391 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
392 # define DP_LINK_BW_1_62 0x06
393 # define DP_LINK_BW_2_7 0x0a
394 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
395 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
397 #define DP_LANE_COUNT_SET 0x101
398 # define DP_LANE_COUNT_MASK 0x0f
401 #define DP_TRAINING_PATTERN_SET 0x102
402 # define DP_TRAINING_PATTERN_DISABLE 0
407 # define DP_TRAINING_PATTERN_MASK 0x3
408 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
411 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
420 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
425 #define DP_TRAINING_LANE0_SET 0x103
426 #define DP_TRAINING_LANE1_SET 0x104
427 #define DP_TRAINING_LANE2_SET 0x105
428 #define DP_TRAINING_LANE3_SET 0x106
430 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
431 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
433 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
434 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
435 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
436 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
439 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
447 #define DP_DOWNSPREAD_CTRL 0x107
451 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
452 # define DP_SET_ANSI_8B10B (1 << 0)
454 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
457 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
458 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
462 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
463 #define DP_LINK_QUAL_LANE1_SET 0x10c
464 #define DP_LINK_QUAL_LANE2_SET 0x10d
465 #define DP_LINK_QUAL_LANE3_SET 0x10e
466 # define DP_LINK_QUAL_PATTERN_DISABLE 0
474 #define DP_TRAINING_LANE0_1_SET2 0x10f
475 #define DP_TRAINING_LANE2_3_SET2 0x110
476 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
481 #define DP_MSTM_CTRL 0x111 /* 1.2 */
482 # define DP_MST_EN (1 << 0)
486 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
487 #define DP_AUDIO_DELAY1 0x113
488 #define DP_AUDIO_DELAY2 0x114
490 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
491 # define DP_LINK_RATE_SET_SHIFT 0
492 # define DP_LINK_RATE_SET_MASK (7 << 0)
494 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
495 # define DP_ALPM_ENABLE (1 << 0)
498 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
499 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
502 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
503 # define DP_PWR_NOT_NEEDED (1 << 0)
505 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
506 # define DP_FEC_READY (1 << 0)
508 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
513 # define DP_FEC_LANE_0_SELECT (0 << 4)
518 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
519 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
521 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
523 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
524 # define DP_PSR_ENABLE (1 << 0)
532 #define DP_ADAPTER_CTRL 0x1a0
533 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
535 #define DP_BRANCH_DEVICE_CTRL 0x1a1
536 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
538 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
539 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
540 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
542 #define DP_SINK_COUNT 0x200
544 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
547 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
548 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
556 #define DP_LANE0_1_STATUS 0x202
557 #define DP_LANE2_3_STATUS 0x203
558 # define DP_LANE_CR_DONE (1 << 0)
566 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
568 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
572 #define DP_SINK_STATUS 0x205
574 #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
577 #define DP_ADJUST_REQUEST_LANE0_1 0x206
578 #define DP_ADJUST_REQUEST_LANE2_3 0x207
579 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
580 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
581 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
583 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
585 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
588 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
590 #define DP_TEST_REQUEST 0x218
591 # define DP_TEST_LINK_TRAINING (1 << 0)
597 #define DP_TEST_LINK_RATE 0x219
598 # define DP_LINK_RATE_162 (0x6)
599 # define DP_LINK_RATE_27 (0xa)
601 #define DP_TEST_LANE_COUNT 0x220
603 #define DP_TEST_PATTERN 0x221
604 # define DP_NO_TEST_PATTERN 0x0
605 # define DP_COLOR_RAMP 0x1
606 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
607 # define DP_COLOR_SQUARE 0x3
609 #define DP_TEST_H_TOTAL_HI 0x222
610 #define DP_TEST_H_TOTAL_LO 0x223
612 #define DP_TEST_V_TOTAL_HI 0x224
613 #define DP_TEST_V_TOTAL_LO 0x225
615 #define DP_TEST_H_START_HI 0x226
616 #define DP_TEST_H_START_LO 0x227
618 #define DP_TEST_V_START_HI 0x228
619 #define DP_TEST_V_START_LO 0x229
621 #define DP_TEST_HSYNC_HI 0x22A
623 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
624 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
626 #define DP_TEST_VSYNC_HI 0x22C
628 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
629 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
631 #define DP_TEST_H_WIDTH_HI 0x22E
632 #define DP_TEST_H_WIDTH_LO 0x22F
634 #define DP_TEST_V_HEIGHT_HI 0x230
635 #define DP_TEST_V_HEIGHT_LO 0x231
637 #define DP_TEST_MISC0 0x232
638 # define DP_TEST_SYNC_CLOCK (1 << 0)
641 # define DP_COLOR_FORMAT_RGB (0 << 1)
646 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
650 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
656 #define DP_TEST_MISC1 0x233
657 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
660 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
662 #define DP_TEST_MISC0 0x232
664 #define DP_TEST_CRC_R_CR 0x240
665 #define DP_TEST_CRC_G_Y 0x242
666 #define DP_TEST_CRC_B_CB 0x244
668 #define DP_TEST_SINK_MISC 0x246
670 # define DP_TEST_COUNT_MASK 0xf
672 #define DP_TEST_PHY_PATTERN 0x248
673 # define DP_TEST_PHY_PATTERN_NONE 0x0
674 # define DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING 0x1
675 # define DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT 0x2
676 # define DP_TEST_PHY_PATTERN_PRBS7 0x3
677 # define DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN 0x4
678 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_1 0x5
679 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_2 0x6
680 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_3 0x7
681 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
682 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
683 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
684 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
685 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
686 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
687 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
688 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
689 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
690 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
692 #define DP_TEST_RESPONSE 0x260
693 # define DP_TEST_ACK (1 << 0)
697 #define DP_TEST_EDID_CHECKSUM 0x261
699 #define DP_TEST_SINK 0x270
700 # define DP_TEST_SINK_START (1 << 0)
702 #define DP_FEC_STATUS 0x280 /* 1.4 */
703 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
706 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
708 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
709 # define DP_FEC_ERROR_COUNT_MASK 0x7F
712 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
713 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
716 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
717 /* up to ID_SLOT_63 at 0x2ff */
719 #define DP_SOURCE_OUI 0x300
720 #define DP_SINK_OUI 0x400
721 #define DP_BRANCH_OUI 0x500
722 #define DP_BRANCH_ID 0x503
723 #define DP_BRANCH_REVISION_START 0x509
724 #define DP_BRANCH_HW_REV 0x509
725 #define DP_BRANCH_SW_REV 0x50A
727 #define DP_SET_POWER 0x600
728 # define DP_SET_POWER_D0 0x1
729 # define DP_SET_POWER_D3 0x2
730 # define DP_SET_POWER_MASK 0x3
731 # define DP_SET_POWER_D3_AUX_ON 0x5
733 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
734 # define DP_EDP_11 0x00
735 # define DP_EDP_12 0x01
736 # define DP_EDP_13 0x02
737 # define DP_EDP_14 0x03
739 #define DP_EDP_GENERAL_CAP_1 0x701
740 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
749 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
750 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
759 #define DP_EDP_GENERAL_CAP_2 0x703
760 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
762 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
763 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
764 # define DP_EDP_X_REGION_CAP_SHIFT 0
765 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
768 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
769 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
775 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
776 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
777 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
778 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
779 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
780 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
787 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
788 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
790 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
791 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
792 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
793 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
795 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
797 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
800 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
801 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
802 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
804 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
805 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
806 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
808 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
809 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
811 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
812 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
814 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
815 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
816 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
817 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
819 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
820 /* 0-5 sink count */
823 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
825 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
826 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
830 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
832 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
833 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
837 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
838 # define DP_PSR_CAPS_CHANGE (1 << 0)
840 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
841 # define DP_PSR_SINK_INACTIVE 0
847 # define DP_PSR_SINK_STATE_MASK 0x07
849 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
850 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
851 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
852 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
855 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
856 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
864 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
865 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
867 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
868 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
869 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
870 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
872 #define DP_DP13_DPCD_REV 0x2200
873 #define DP_DP13_MAX_LINK_RATE 0x2201
875 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
876 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
886 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
887 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
891 #define DP_CEC_TUNNELING_CONTROL 0x3001
892 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
895 #define DP_CEC_RX_MESSAGE_INFO 0x3002
896 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
897 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
903 #define DP_CEC_TX_MESSAGE_INFO 0x3003
904 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
905 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
906 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
910 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
911 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
918 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
919 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
927 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
928 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
937 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
938 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
939 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
941 #define DP_AUX_HDCP_BKSV 0x68000
942 #define DP_AUX_HDCP_RI_PRIME 0x68005
943 #define DP_AUX_HDCP_AKSV 0x68007
944 #define DP_AUX_HDCP_AN 0x6800C
945 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + (h) * 4)
946 #define DP_AUX_HDCP_BCAPS 0x68028
948 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
949 #define DP_AUX_HDCP_BSTATUS 0x68029
953 # define DP_BSTATUS_READY BIT(0)
954 #define DP_AUX_HDCP_BINFO 0x6802A
955 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
956 #define DP_AUX_HDCP_AINFO 0x6803B
960 #define DP_PEER_DEVICE_NONE 0x0
961 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
962 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
963 #define DP_PEER_DEVICE_SST_SINK 0x3
964 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
967 #define DP_LINK_ADDRESS 0x01
968 #define DP_CONNECTION_STATUS_NOTIFY 0x02
969 #define DP_ENUM_PATH_RESOURCES 0x10
970 #define DP_ALLOCATE_PAYLOAD 0x11
971 #define DP_QUERY_PAYLOAD 0x12
972 #define DP_RESOURCE_STATUS_NOTIFY 0x13
973 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
974 #define DP_REMOTE_DPCD_READ 0x20
975 #define DP_REMOTE_DPCD_WRITE 0x21
976 #define DP_REMOTE_I2C_READ 0x22
977 #define DP_REMOTE_I2C_WRITE 0x23
978 #define DP_POWER_UP_PHY 0x24
979 #define DP_POWER_DOWN_PHY 0x25
980 #define DP_SINK_EVENT_NOTIFY 0x30
981 #define DP_QUERY_STREAM_ENC_STATUS 0x38
984 #define DP_NAK_WRITE_FAILURE 0x01
985 #define DP_NAK_INVALID_READ 0x02
986 #define DP_NAK_CRC_FAILURE 0x03
987 #define DP_NAK_BAD_PARAM 0x04
988 #define DP_NAK_DEFER 0x05
989 #define DP_NAK_LINK_FAILURE 0x06
990 #define DP_NAK_NO_RESOURCES 0x07
991 #define DP_NAK_DPCD_FAIL 0x08
992 #define DP_NAK_I2C_NAK 0x09
993 #define DP_NAK_ALLOCATE_FAIL 0x0a
1001 #define DP_MST_PHYSICAL_PORT_0 0
1014 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
1015 #define DP_RECEIVER_CAP_SIZE 0xf
1025 #define DP_SDP_AUDIO_TIMESTAMP 0x01
1026 #define DP_SDP_AUDIO_STREAM 0x02
1027 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1028 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1029 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
1030 #define DP_SDP_VSC 0x07 /* DP 1.2 */
1031 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1032 #define DP_SDP_PPS 0x10 /* DP 1.4 */
1033 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1034 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1035 /* 0x80+ CEA-861 infoframe types */
1040 u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */
1044 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
1045 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1046 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1051 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
1052 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
1054 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
1056 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
1061 #define EDP_VSC_PSR_STATE_ACTIVE (1 << 0)
1066 DP_PIXELFORMAT_RGB = 0,
1067 DP_PIXELFORMAT_YUV444 = 0x1,
1068 DP_PIXELFORMAT_YUV422 = 0x2,
1069 DP_PIXELFORMAT_YUV420 = 0x3,
1070 DP_PIXELFORMAT_Y_ONLY = 0x4,
1071 DP_PIXELFORMAT_RAW = 0x5,
1072 DP_PIXELFORMAT_RESERVED = 0x6,
1076 DP_COLORIMETRY_DEFAULT = 0,
1077 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1078 DP_COLORIMETRY_BT709_YCC = 0x1,
1079 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1080 DP_COLORIMETRY_XVYCC_601 = 0x2,
1081 DP_COLORIMETRY_OPRGB = 0x3,
1082 DP_COLORIMETRY_XVYCC_709 = 0x3,
1083 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1084 DP_COLORIMETRY_SYCC_601 = 0x4,
1085 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1086 DP_COLORIMETRY_OPYCC_601 = 0x5,
1087 DP_COLORIMETRY_BT2020_RGB = 0x6,
1088 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1089 DP_COLORIMETRY_BT2020_YCC = 0x7,
1093 DP_DYNAMIC_RANGE_VESA = 0,
1098 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1099 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1100 DP_CONTENT_TYPE_PHOTO = 0x02,
1101 DP_CONTENT_TYPE_VIDEO = 0x03,
1102 DP_CONTENT_TYPE_GAME = 0x04,
1131 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
1138 return dpcd[DP_DPCD_REV] >= 0x12 && in drm_dp_tps3_supported()
1145 return dpcd[DP_DPCD_REV] >= 0x14 && in drm_dp_tps4_supported()
1152 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : in drm_dp_training_pattern_mask()