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Searched +full:0 +full:x40000000 (Results 1 – 25 of 48) sorted by relevance

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/optee_os/core/arch/arm/plat-imx/
H A Dconf.mk181 CFG_DRAM_BASE ?= 0x40000000
188 CFG_DRAM_BASE ?= 0x40000000
195 CFG_DRAM_BASE ?= 0x40000000
202 CFG_DRAM_BASE ?= 0x40000000
209 CFG_DRAM_BASE ?= 0x80000000
217 CFG_DRAM_BASE ?= 0x80000000
225 CFG_DRAM_BASE ?= 0x80000000
232 CFG_DRAM_BASE ?= 0x80000000
242 CFG_DRAM_BASE ?= 0x80000000
255 CFG_DRAM_BASE ?= 0x80000000
[all …]
H A Dtzc380.c25 #define TZASC2_BASE 0
35 vaddr_t addr_imx = 0; in imx_tzc_auto_configure()
39 * has the memory regions starting at address 0x0 instead of the DRAM in imx_tzc_auto_configure()
40 * base address (0x40000000) in imx_tzc_auto_configure()
52 vaddr_t addr[2] = {0}; in imx_configure_tzasc()
54 int i = 0; in imx_configure_tzasc()
56 addr[0] = core_mmu_get_va(TZASC_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
60 assert(TZASC2_BASE != 0); in imx_configure_tzasc()
65 for (i = 0; i < end; i++) { in imx_configure_tzasc()
/optee_os/core/arch/arm/plat-stm/
H A Dconf.mk22 CFG_DDR_START ?= 0x40000000
23 CFG_DDR_SIZE ?= 0x40000000
24 CFG_STM_RSV_DRAM_STARTBYTES ?= 0
25 CFG_CORE_TZSRAM_EMUL_START ?= 0x7fe00000
26 CFG_DDR_TEETZ_RESERVED_START ?= 0x7e000000
27 CFG_DDR_TEETZ_RESERVED_SIZE ?= 0x01e00000
31 CFG_DDR_START ?= 0x40000000
32 CFG_DDR_SIZE ?= 0x80000000
33 CFG_STM_RSV_DRAM_STARTBYTES ?= 0x02000000
34 CFG_CORE_TZSRAM_EMUL_START ?= 0x94a00000
[all …]
H A Dplatform_config.h16 #define CPU_IOMEM_BASE 0x08760000
17 #define CPU_IOMEM_SIZE 0x000a0000
18 #define CPU_PORT_FILT_START 0x40000000
19 #define CPU_PORT_FILT_END 0xC0000000
20 #define STXHXXX_LPM_PERIPH_BASE 0x09700000
21 #define RNG_BASE 0x08A89000
22 #define RNG_SIZE 0x00001000
29 #define CPU_IOMEM_BASE 0x08760000
30 #define CPU_IOMEM_SIZE 0x000a0000
31 #define CPU_PORT_FILT_START 0x40000000
[all …]
/optee_os/lib/libutils/isoc/arch/arm/softfloat/source/
H A Ds_subMagsF32.c65 if ( 0 < expDiff ) goto expABigger; in softfloat_subMagsF32()
66 if ( expDiff < 0 ) goto expBBigger; in softfloat_subMagsF32()
67 if ( expA == 0xFF ) { in softfloat_subMagsF32()
79 uiZ = packToF32UI( softfloat_roundingMode == softfloat_round_min, 0, 0 ); in softfloat_subMagsF32()
82 if ( expB == 0xFF ) { in softfloat_subMagsF32()
84 uiZ = packToF32UI( signZ ^ 1, 0xFF, 0 ); in softfloat_subMagsF32()
87 sigA += expA ? 0x40000000 : sigA; in softfloat_subMagsF32()
89 sigB |= 0x40000000; in softfloat_subMagsF32()
96 if ( expA == 0xFF ) { in softfloat_subMagsF32()
101 sigB += expB ? 0x40000000 : sigB; in softfloat_subMagsF32()
[all …]
H A Ds_addMagsF32.c65 if ( expA == 0xFF ) { in softfloat_addMagsF32()
71 uiZ = packToF32UI( signZ, 0, (uiA + uiB) & 0x7FFFFFFF ); in softfloat_addMagsF32()
75 sigZ = 0x40000000 + sigA + sigB; in softfloat_addMagsF32()
77 if ( expDiff < 0 ) { in softfloat_addMagsF32()
78 if ( expB == 0xFF ) { in softfloat_addMagsF32()
80 uiZ = packToF32UI( signZ, 0xFF, 0 ); in softfloat_addMagsF32()
84 sigA += expA ? 0x20000000 : sigA; in softfloat_addMagsF32()
87 if ( expA == 0xFF ) { in softfloat_addMagsF32()
93 sigB += expB ? 0x20000000 : sigB; in softfloat_addMagsF32()
96 sigZ = 0x20000000 + sigA + sigB; in softfloat_addMagsF32()
[all …]
H A Df64_to_f32.c61 if ( exp == 0x7FF ) { in f64_to_f32()
66 uiZ = packToF32UI( sign, 0xFF, 0 ); in f64_to_f32()
72 uiZ = packToF32UI( sign, 0, 0 ); in f64_to_f32()
75 return softfloat_roundPackToF32( sign, exp - 0x381, sig32 | 0x40000000 ); in f64_to_f32()
H A Df128_to_f32.c61 sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0); in f128_to_f32()
62 if ( exp == 0x7FFF ) { in f128_to_f32()
67 uiZ = packToF32UI( sign, 0xFF, 0 ); in f128_to_f32()
73 uiZ = packToF32UI( sign, 0, 0 ); in f128_to_f32()
76 exp -= 0x3F81; in f128_to_f32()
78 if ( exp < -0x1000 ) exp = -0x1000; in f128_to_f32()
80 return softfloat_roundPackToF32( sign, exp, sig32 | 0x40000000 ); in f128_to_f32()
H A Df128M_to_f32.c73 | ((aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )]) != 0); in f128M_to_f32()
74 if ( exp == 0x7FFF ) { in f128M_to_f32()
79 uiZ = packToF32UI( sign, 0xFF, 0 ); in f128M_to_f32()
85 uiZ = packToF32UI( sign, 0, 0 ); in f128M_to_f32()
88 exp -= 0x3F81; in f128M_to_f32()
90 if ( exp < -0x1000 ) exp = -0x1000; in f128M_to_f32()
92 return softfloat_roundPackToF32( sign, exp, sig32 | 0x40000000 ); in f128M_to_f32()
/optee_os/core/arch/arm/plat-rzn1/
H A Dplatform_config.h13 #define DRAM_BASE 0x80000000
14 #define DRAM_SIZE 0x40000000 /* 1GB, and support 256MB */
17 #define GIC_BASE 0x44100000
18 #define GICD_OFFSET 0x1000
19 #define GICC_OFFSET 0x2000
24 #define PERIPH_REG_BASE 0x40000000
27 #define SYSCTRL_BASE 0x4000C000
30 #define CONSOLE_UART_BASE 0x40060000
/optee_os/core/arch/arm/plat-rcar/
H A Dplatform_config.h41 #define GIC_BASE 0xF1000000
42 #define GICC_BASE 0xF1020000
43 #define GICD_BASE 0xF1010000
45 #define CONSOLE_UART_BASE 0xE6E88000
47 #define PRR_BASE 0xFFF00000
51 #define GICC_BASE 0xF1060000
52 #define GICD_BASE 0xF1000000
55 #define CONSOLE_UART_BASE 0xE6C50000
57 #define CONSOLE_UART_BASE 0xE6540000
63 #define NSEC_DDR_0_BASE 0x47E00000
[all …]
/optee_os/core/arch/arm/plat-aspeed/
H A Dconf.mk14 CFG_DRAM_BASE ?= 0x80000000
15 CFG_DRAM_SIZE ?= 0x40000000
17 CFG_TZDRAM_START ?= 0xb0000000
18 CFG_TZDRAM_SIZE ?= 0x1000000
24 include core/arch/arm/cpu/cortex-armv8-0.mk
38 CFG_DRAM_BASE ?= 0x400000000
39 CFG_DRAM_SIZE ?= 0x40000000
41 CFG_TZDRAM_START ?= 0x430080000
42 CFG_TZDRAM_SIZE ?= 0x1000000
/optee_os/core/arch/arm/dts/
H A Dfsl-lx2160a.dtsi10 /memreserve/ 0x80000000 0x00010000;
24 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x0>;
32 clocks = <&clockgen 1 0>;
33 d-cache-size = <0x8000>;
36 i-cache-size = <0xC000>;
48 reg = <0x1>;
49 clocks = <&clockgen 1 0>;
50 d-cache-size = <0x8000>;
[all …]
/optee_os/core/arch/arm/plat-mediatek/
H A Dconf.mk5 include core/arch/arm/cpu/cortex-armv8-0.mk
12 CFG_DRAM_BASE ?= 0x40000000
15 CFG_DRAM_SIZE ?= 0x40000000
25 CFG_TZDRAM_START ?= 0xbe000000
26 CFG_TZDRAM_SIZE ?= 0x01e00000
27 CFG_SHMEM_START ?= 0xbfe00000
28 CFG_SHMEM_SIZE ?= 0x00200000
36 CFG_TZDRAM_START ?= 0x43200000
37 CFG_TZDRAM_SIZE ?= 0x00a00000
39 CFG_SHMEM_SIZE ?= 0x00200000
[all …]
H A Dplatform_config.h22 #define GIC_BASE 0x10220000
23 #define GICC_OFFSET 0x2000
24 #define GICD_OFFSET 0x1000
26 #define UART0_BASE 0x11002000
27 #define UART1_BASE 0x11003000
28 #define UART2_BASE 0x11004000
29 #define UART3_BASE 0x11005000
35 #define DRAM0_BASE 0x40000000
36 #define DRAM0_SIZE 0x80000000
40 #define GIC_BASE 0x0C000000
[all …]
/optee_os/core/arch/arm/plat-nuvoton/
H A Dplatform_config.h14 #define DRAM0_BASE 0x00000000
15 #define DRAM0_SIZE 0x40000000 /* 1G DDR */
16 #define GIC_BASE 0xDFFF8000
17 #define UART0_BASE 0xf0000000
18 #define UART_REG_SIZE 0x100
20 #define GICD_OFFSET 0x1000
21 #define GICC_OFFSET 0x2000
/optee_os/core/arch/arm/plat-sunxi/
H A Dconf.mk19 CFG_NS_ENTRY_ADDR ?= 0x42000000
23 CFG_TZDRAM_START ?= 0x5c000000
24 CFG_TZDRAM_SIZE ?= 0x03e00000
25 CFG_SHMEM_START ?= 0x5fe00000
26 CFG_SHMEM_SIZE ?= 0x00200000
30 include core/arch/arm/cpu/cortex-armv8-0.mk
33 CFG_TZDRAM_START ?= 0x40000000
34 CFG_TZDRAM_SIZE ?= 0x2000000
35 CFG_SHMEM_START ?= 0x44000000
36 CFG_SHMEM_SIZE ?= 0x00400000
/optee_os/core/arch/arm/plat-uniphier/
H A Dconf.mk3 include core/arch/arm/cpu/cortex-armv8-0.mk
8 CFG_DRAM0_BASE ?= 0x80000000
9 CFG_DRAM0_SIZE ?= 0xc0000000
10 CFG_DRAM0_RSV_SIZE ?= 0x02000000
15 CFG_DRAM0_BASE ?= 0x80000000
16 CFG_DRAM0_SIZE ?= 0x40000000
17 CFG_DRAM0_RSV_SIZE ?= 0x02000000
20 CFG_TZDRAM_START ?= (CFG_DRAM0_BASE + 0x01080000)
21 CFG_TZDRAM_SIZE ?= 0x00E00000
22 CFG_SHMEM_START ?= (CFG_DRAM0_BASE + 0x00E00000)
[all …]
/optee_os/core/arch/arm/plat-imx/registers/
H A Dimx7ulp.h11 #define GIC_BASE 0x40020000
12 #define GIC_SIZE 0x8000
13 #define GICC_OFFSET 0x2000
14 #define GICD_OFFSET 0x1000
16 #define AIPS0_BASE 0x40000000
17 #define AIPS0_SIZE 0x800000
18 #define AIPS1_BASE 0x40800000
19 #define AIPS1_SIZE 0x800000
20 #define M4_AIPS_BASE 0x41000000
21 #define M4_AIPS_SIZE 0x100000
[all …]
/optee_os/core/arch/arm/plat-hikey/
H A Dconf.mk3 include core/arch/arm/cpu/cortex-armv8-0.mk
35 CFG_TEE_SDP_MEM_BASE ?= 0x3E800000
36 CFG_TEE_SDP_MEM_SIZE ?= 0x00400000
48 CFG_ASAN_SHADOW_OFFSET ?= 0x372E38E0
56 CFG_TZDRAM_START ?= 0x3F000000
57 CFG_TZDRAM_SIZE ?= 0x01000000
58 CFG_SHMEM_START ?= 0x3EE00000
59 CFG_SHMEM_SIZE ?= 0x00200000
60 CFG_TEE_RAM_VA_SIZE ?= 0x00200000
61 CFG_DRAM1_BASE ?= 0x40000000
/optee_os/core/arch/arm/plat-rpi3/
H A Dplatform_config.h44 #define CONSOLE_UART_BASE 0x3f215040 /* UART0 */
55 * 0x0a00_0000
57 * 0x0842_0000 | TZDRAM
59 * 0x0840_0000 [ARM Trusted Firmware ] -
60 * 0x0840_0000 [TZDRAM_BASE, BL32_LOAD_ADDR] -
62 * 0x0800_0000 | DRAM0
64 * 0x0000_0000 [DRAM0_BASE] -
68 #define DRAM0_BASE 0x00000000
69 #define DRAM0_SIZE 0x40000000
/optee_os/core/arch/arm/plat-stm32mp2/
H A Dplatform_config.h15 #define APB1_BASE 0x40000000
16 #define APB1_SIZE 0x00200000
17 #define APB2_BASE 0x40200000
18 #define APB2_SIZE 0x00040000
19 #define AHB2_BASE 0x40400000
20 #define AHB2_SIZE 0x01c00000
21 #define AHB3_BASE 0x42000000
22 #define AHB3_SIZE 0x02000000
23 #define APB3_BASE 0x44000000
24 #define APB3_SIZE 0x001f0000
[all …]
/optee_os/core/arch/arm/include/kernel/
H A Dtz_proc_def.h18 #define CP15_CONFIG_CPU_ID_MASK U(0x00000003)
19 #define CPU_ID0 U(0x00000000)
20 #define CPU_ID1 U(0x00000001)
25 #define CP15_CONFIG_NS_MASK U(0x00000001)
26 #define CP15_CONFIG_IRQ_MASK U(0x00000002)
27 #define CP15_CONFIG_FIQ_MASK U(0x00000004)
28 #define CP15_CONFIG_EA_MASK U(0x00000008)
29 #define CP15_CONFIG_FW_MASK U(0x00000010)
30 #define CP15_CONFIG_AW_MASK U(0x00000020)
31 #define CP15_CONFIG_nET_MASK U(0x00000040)
[all …]
/optee_os/core/arch/arm/include/sm/
H A Dpsci.h12 #define PSCI_VERSION_0_2 U(0x00000002)
13 #define PSCI_VERSION_1_0 U(0x00010000)
14 #define PSCI_VERSION_1_1 U(0x00010001)
15 #define PSCI_VERSION U(0x84000000)
16 #define PSCI_CPU_SUSPEND U(0x84000001)
17 #define PSCI_CPU_OFF U(0x84000002)
18 #define PSCI_CPU_ON U(0x84000003)
19 #define PSCI_CPU_ON_SMC64 (PSCI_CPU_ON | U(0x40000000))
20 #define PSCI_AFFINITY_INFO U(0x84000004)
21 #define PSCI_MIGRATE U(0x84000005)
[all …]
/optee_os/core/arch/arm/plat-poplar/
H A Dplatform_config.h29 * 0xFF00_0000 [DRAM2_LIMIT]
31 * 0xF000_0000 [DRAM2_BASE]
33 * 0x8000_0000 (0x4000_0000 for 1GB board) [DRAM0_LIMIT]
35 * 0x3700_0000 CONFIG_SYS_TEXT_BASE (u-boot)
38 * 0x3240_0000
40 * 0x3220_0000
42 * 0x3200_0000
44 * 0x3000_0000
46 * 0x0480_0000 CONFIG_SYS_LOAD_ADDR (defined in u-boot)
48 * 0x0420_0000 CONFIG_SYS_INIT_SP_ADDR (defined in u-boot)
[all …]

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