| #
4e9f4c98 |
| 28-Nov-2023 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
arm: aspeed: Add cflags for AST2600 SoCs
AST2600 only supports VFPv3-D16, which should be speicifed by cflags
to prevent undef-abort due to unsupoorted instructions generated by
compilers.
Signed-o
arm: aspeed: Add cflags for AST2600 SoCs
AST2600 only supports VFPv3-D16, which should be speicifed by cflags
to prevent undef-abort due to unsupoorted instructions generated by
compilers.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Neal Liu <neal_liu@aspeedtech.com>
show more ...
|
| #
cff92aa4 |
| 29-Aug-2023 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
arm: aspeed: Update secure memory layout
Update the TZDRAM region based on the 1GB DRAM space of
Aspeed AST2600/AST2700 EVBs.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Je
arm: aspeed: Update secure memory layout
Update the TZDRAM region based on the 1GB DRAM space of
Aspeed AST2600/AST2700 EVBs.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| #
ba69abea |
| 16-Feb-2023 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
arm: Add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU.
This patch adds the platform support for AST2700 to execute
64-bits OP-TEE on top of ARMv8 TrustZo
arm: Add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 CPU.
This patch adds the platform support for AST2700 to execute
64-bits OP-TEE on top of ARMv8 TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
show more ...
|
| #
63bd5b26 |
| 20-Jan-2022 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
arm: Add Aspeed AST2600 platform support
Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone feat
arm: Add Aspeed AST2600 platform support
Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|