1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2023, STMicroelectronics 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 32 13 14 /* SoC interface registers base address ranges */ 15 #define APB1_BASE 0x40000000 16 #define APB1_SIZE 0x00200000 17 #define APB2_BASE 0x40200000 18 #define APB2_SIZE 0x00040000 19 #define AHB2_BASE 0x40400000 20 #define AHB2_SIZE 0x01c00000 21 #define AHB3_BASE 0x42000000 22 #define AHB3_SIZE 0x02000000 23 #define APB3_BASE 0x44000000 24 #define APB3_SIZE 0x001f0000 25 #define AHB4_BASE 0x44200000 26 #define AHB4_SIZE 0x01e00000 27 #define SAPB_BASE 0x46000000 28 #define SAPB_SIZE 0x00200000 29 #define SAHB_BASE 0x46200000 30 #define SAHB_SIZE 0x01e00000 31 #define APB4_BASE 0x48000000 32 #define APB4_SIZE 0x00200000 33 #define AHB5_BASE 0x48200000 34 #define AHB5_SIZE 0x01e00000 35 36 /* SoC interface registers base address */ 37 #define UART2_BASE 0x400e0000 38 #define UART3_BASE 0x400f0000 39 #define UART4_BASE 0x40100000 40 #define UART5_BASE 0x40110000 41 #define I2C4_BASE 0x40150000 42 #define I2C6_BASE 0x40170000 43 #define UART6_BASE 0x40220000 44 #define UART9_BASE 0x402c0000 45 #define UART1_BASE 0x40330000 46 #define SPI6_BASE 0x40350000 47 #define UART7_BASE 0x40370000 48 #define UART8_BASE 0x40380000 49 #define OSPI1_BASE 0x40430000 50 #define OSPI2_BASE 0x40440000 51 #define HASH1_BASE 0x42010000 52 #define RNG1_BASE 0x42020000 53 #define CRYP1_BASE 0x42030000 54 #define SAES_BASE 0x42050000 55 #define PKA_BASE 0x42060000 56 #define RIFSC_BASE 0x42080000 57 #define RISAF4_BASE 0x420d0000 58 #define RISAF5_BASE 0x420e0000 59 #define RISAB1_BASE 0x420f0000 60 #define RISAB2_BASE 0x42100000 61 #define RISAB6_BASE 0x42140000 62 #define BSEC3_BASE 0x44000000 63 #define IWDG2_BASE 0x44002000 64 #define IWDG1_BASE 0x44010000 65 #define RCC_BASE 0x44200000 66 #define PWR_BASE 0x44210000 67 #define SYSCFG_BASE 0x44230000 68 #define GPIOA_BASE 0x44240000 69 #define GPIOB_BASE 0x44250000 70 #define GPIOC_BASE 0x44260000 71 #define GPIOD_BASE 0x44270000 72 #define GPIOE_BASE 0x44280000 73 #define GPIOF_BASE 0x44290000 74 #define GPIOG_BASE 0x442a0000 75 #define GPIOH_BASE 0x442b0000 76 #define GPIOI_BASE 0x442c0000 77 #define GPIOJ_BASE 0x442d0000 78 #define GPIOK_BASE 0x442e0000 79 #define RTC_BASE 0x46000000 80 #define TAMP_BASE 0x46010000 81 #define GPIOZ_BASE 0x46200000 82 #define STGEN_BASE 0x48080000 83 #define FMC_BASE 0x48200000 84 #define PCIE_BASE 0x48400000 85 #define A35SSC_BASE 0x48800000 86 #define GIC_BASE 0x4ac00000 87 #define DDR_BASE UL(0x80000000) 88 89 #define SYSRAM_BASE 0x0e000000 90 91 #define SRAM1_BASE 0x0e040000 92 93 /* GIC resources */ 94 #define GIC_SIZE 0x80000 95 #define GICC_OFFSET 0x20000 96 #define GICD_OFFSET 0x10000 97 98 /* Console configuration */ 99 #define GIC_SPI_UART4 126 100 101 #define TARGET_CPU0_GIC_MASK BIT(0) 102 #define TARGET_CPU1_GIC_MASK BIT(1) 103 #define TARGET_CPUS_GIC_MASK GENMASK_32(CFG_TEE_CORE_NB_CORE - 1, 0) 104 105 /* USART/UART resources */ 106 #define USART1_BASE UART1_BASE 107 #define USART2_BASE UART2_BASE 108 #define USART3_BASE UART3_BASE 109 #define USART6_BASE UART6_BASE 110 111 #endif /*PLATFORM_CONFIG_H*/ 112