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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mn-var-som-symphony.dts18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
53 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
66 pinctrl-0 = <&pinctrl_i2c2>;
71 reg = <0x20>;
74 pinctrl-0 = <&pinctrl_pca9534>;
105 reg = <0x3d>;
109 pinctrl-0 = <&pinctrl_ptn5150>;
118 reg = <0x38>;
120 pinctrl-0 = <&pinctrl_captouch>;
132 reg = <0x68>;
[all …]
H A Dimx8mn-var-som.dtsi20 reg = <0x0 0x40000000 0 0x40000000>;
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
53 pinctrl-0 = <&pinctrl_ecspi1>;
55 <&gpio1 0 GPIO_ACTIVE_LOW>;
61 touchscreen@0 {
62 reg = <0>;
65 pinctrl-0 = <&pinctrl_restouch>;
89 pinctrl-0 = <&pinctrl_fec1>;
99 #size-cells = <0>;
113 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
H A Dimx8mm-var-som.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
25 pinctrl-0 = <&pinctrl_reg_eth_phy>;
72 pinctrl-0 = <&pinctrl_ecspi1>;
74 <&gpio1 0 GPIO_ACTIVE_LOW>;
80 touchscreen@0 {
81 reg = <0>;
84 pinctrl-0 = <&pinctrl_restouch>;
108 pinctrl-0 = <&pinctrl_fec1>;
117 #size-cells = <0>;
132 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
H A Dimx8mm-var-som-symphony.dts17 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28 pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
63 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
76 pinctrl-0 = <&pinctrl_i2c2>;
81 reg = <0x20>;
84 pinctrl-0 = <&pinctrl_pca9534>;
115 reg = <0x3d>;
119 pinctrl-0 = <&pinctrl_ptn5150>;
128 reg = <0x38>;
130 pinctrl-0 = <&pinctrl_captouch>;
[all …]
H A Dimx8mp-evk.dts21 pinctrl-0 = <&pinctrl_gpio_led>;
32 reg = <0x0 0x40000000 0 0xc0000000>,
33 <0x1 0x00000000 0 0xc0000000>;
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
50 pinctrl-0 = <&pinctrl_fec>;
58 #size-cells = <0>;
74 pinctrl-0 = <&pinctrl_i2c3>;
79 reg = <0x20>;
92 pinctrl-0 = <&pinctrl_uart2>;
100 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
[all …]
H A Dimx8mm-beacon-som.dtsi10 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
19 reg = <0x0 0x40000000 0 0x80000000>;
49 pinctrl-0 = <&pinctrl_fec1>;
57 #size-cells = <0>;
59 ethphy0: ethernet-phy@0 {
61 reg = <0>;
69 pinctrl-0 = <&pinctrl_i2c1>;
74 reg = <0x4b>;
76 pinctrl-0 = <&pinctrl_pmic>;
184 pinctrl-0 = <&pinctrl_i2c3>;
[all …]
H A Dimx8mm-beacon-baseboard.dtsi30 pinctrl-0 = <&pinctrl_led3>;
72 pinctrl-0 = <&pinctrl_espi2>;
76 eeprom@0 {
78 reg = <0>;
91 pinctrl-0 = <&pinctrl_i2c2>;
98 pinctrl-0 = <&pinctrl_i2c4>;
103 reg = <0x1a>;
115 0x0000 /* 0:Default */
116 0x0000 /* 1:Default */
117 0x0000 /* 2:FN_DMICCLK */
[all …]
H A Dimx8mn-evk.dtsi17 pinctrl-0 = <&pinctrl_gpio_led>;
28 reg = <0x0 0x40000000 0 0x80000000>;
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
45 pinctrl-0 = <&pinctrl_fec1>;
53 #size-cells = <0>;
55 ethphy0: ethernet-phy@0 {
57 reg = <0>;
65 pinctrl-0 = <&pinctrl_i2c1>;
72 pinctrl-0 = <&pinctrl_i2c2>;
78 pinctrl-0 = <&pinctrl_typec1>;
[all …]
/OK3568_Linux_fs/kernel/drivers/media/usb/go7007/
H A Ds2250-board.c26 #define TLV320_ADDRESS 0x34
27 #define VPX322_ADDR_ANALOGCONTROL1 0x02
28 #define VPX322_ADDR_BRIGHTNESS0 0x0127
29 #define VPX322_ADDR_BRIGHTNESS1 0x0131
30 #define VPX322_ADDR_CONTRAST0 0x0128
31 #define VPX322_ADDR_CONTRAST1 0x0132
32 #define VPX322_ADDR_HUE 0x00dc
33 #define VPX322_ADDR_SAT 0x0030
50 0x1e, 0x00,
51 0x00, 0x17,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/amlogic/
H A Damlogic,meson-gx-ao-secure.yaml52 reg = <0x140 0x140>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx8mn-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
H A Dfsl,imx8mm-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
/OK3568_Linux_fs/kernel/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
H A Dpinctrl-exynos-arm64.c24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
49 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
50 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
51 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
52 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
53 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
54 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-sparx5.c22 #define CPU_REGS_GENERAL_CTRL (0x22 * 4)
27 #define CPU_REGS_PROC_CTRL (0x2C * 4)
33 #define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
34 #define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
35 #define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
37 #define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
80 pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value); in sparx5_set_cacheable()
109 pr_debug("%s: Set EMMC_CTRL: 0x%08x\n", in sdhci_sparx5_set_emmc()
152 .quirks = 0,
198 (value > 0 && value <= MSHC_DLY_CC_MAX)) in sdhci_sparx5_probe()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/pci/
H A Dpci-vr41xx.h12 #define PCIU_BASE 0x0f000c00UL
13 #define PCIU_SIZE 0x200UL
15 #define PCIMMAW1REG 0x00
16 #define PCIMMAW2REG 0x04
17 #define PCITAW1REG 0x08
18 #define PCITAW2REG 0x0c
19 #define PCIMIOAWREG 0x10
20 #define IBA(addr) ((addr) & 0xff000000U)
21 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
22 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dam335x-draco.dts45 reg = <0x4b000000 1000000>;
53 pinctrl-0 = <&gpio_mux_pins>;
57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */
58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */
59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */
60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */
61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */
67 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_plck FIX STO should be a OUTPUT driven high*/
68 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
69 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.mii1_txen */
[all …]
/OK3568_Linux_fs/kernel/arch/sparc/lib/
H A Dbzero.S14 and %o1, 0xff, %o3
30 prefetch [%o0 + 0x000], #n_writes
31 andcc %o0, 0x3, %g0
33 1: stb %o2, [%o0 + 0x00]
35 andcc %o0, 0x3, %g0
38 2: andcc %o0, 0x7, %g0
40 stw %o2, [%o0 + 0x00]
43 3: and %o1, 0x38, %g1
44 cmp %o1, 0x40
45 andn %o1, 0x3f, %o4
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dmvebu_lcd.c16 #define MVEBU_LCD_WIN_CONTROL(w) (MVEBU_LCD_BASE + 0xf000 + ((w) << 4))
17 #define MVEBU_LCD_WIN_BASE(w) (MVEBU_LCD_BASE + 0xf004 + ((w) << 4))
18 #define MVEBU_LCD_WIN_REMAP(w) (MVEBU_LCD_BASE + 0xf00c + ((w) << 4))
20 #define MVEBU_LCD_CFG_DMA_START_ADDR_0 (MVEBU_LCD_BASE + 0x00cc)
21 #define MVEBU_LCD_CFG_DMA_START_ADDR_1 (MVEBU_LCD_BASE + 0x00dc)
23 #define MVEBU_LCD_CFG_GRA_START_ADDR0 (MVEBU_LCD_BASE + 0x00f4)
24 #define MVEBU_LCD_CFG_GRA_START_ADDR1 (MVEBU_LCD_BASE + 0x00f8)
25 #define MVEBU_LCD_CFG_GRA_PITCH (MVEBU_LCD_BASE + 0x00fc)
26 #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x0100)
27 #define MVEBU_LCD_SPU_GRA_HPXL_VLN (MVEBU_LCD_BASE + 0x0104)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun6i.h18 u32 cr; /* 0x00 */
19 u32 ccr; /* 0x04 controller configuration register */
20 u32 dbgcr; /* 0x08 */
21 u32 dbgcr1; /* 0x0c */
22 u32 rmcr[8]; /* 0x10 */
23 u32 mmcr[16]; /* 0x30 */
24 u32 mbagcr[6]; /* 0x70 */
25 u32 maer; /* 0x88 */
26 u8 res0[0x14]; /* 0x8c */
27 u32 mdfscr; /* 0x100 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dusb.h13 /* 0x000 */
19 /* 0x010 */
24 /* 0x020 */
27 /* 0x100 */
34 /* 0x120 */
40 /* 0x130 */
43 /* 0x140 */
49 /* 0x150 */
55 /* 0x160 */
61 /* 0x170 */
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/renesas/
H A Dr8a77995-sysc.c15 { "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca53-scu", 0x140, 0, R8A77995_PD_CA53_SCU, R8A77995_PD_ALWAYS_ON,
18 { "ca53-cpu0", 0x200, 0, R8A77995_PD_CA53_CPU0, R8A77995_PD_CA53_SCU,
H A Dr8a7779-sysc.c15 { "always-on", 0, 0, R8A7779_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "arm1", 0x40, 1, R8A7779_PD_ARM1, R8A7779_PD_ALWAYS_ON,
18 { "arm2", 0x40, 2, R8A7779_PD_ARM2, R8A7779_PD_ALWAYS_ON,
20 { "arm3", 0x40, 3, R8A7779_PD_ARM3, R8A7779_PD_ALWAYS_ON,
22 { "sgx", 0xc0, 0, R8A7779_PD_SGX, R8A7779_PD_ALWAYS_ON },
23 { "vdp", 0x100, 0, R8A7779_PD_VDP, R8A7779_PD_ALWAYS_ON },
24 { "imp", 0x140, 0, R8A7779_PD_IMP, R8A7779_PD_ALWAYS_ON },
H A Dr8a7792-sysc.c16 { "always-on", 0, 0, R8A7792_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
17 { "ca15-scu", 0x180, 0, R8A7792_PD_CA15_SCU, R8A7792_PD_ALWAYS_ON,
19 { "ca15-cpu0", 0x40, 0, R8A7792_PD_CA15_CPU0, R8A7792_PD_CA15_SCU,
21 { "ca15-cpu1", 0x40, 1, R8A7792_PD_CA15_CPU1, R8A7792_PD_CA15_SCU,
23 { "sgx", 0xc0, 0, R8A7792_PD_SGX, R8A7792_PD_ALWAYS_ON },
24 { "imp", 0x140, 0, R8A7792_PD_IMP, R8A7792_PD_ALWAYS_ON },
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Dphy_ac.h7 #define B43_PHY_AC_BBCFG 0x001
8 #define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */
9 #define B43_PHY_AC_BANDCTL 0x003 /* Band control */
10 #define B43_PHY_AC_BANDCTL_5GHZ 0x0001
11 #define B43_PHY_AC_TABLE_ID 0x00d
12 #define B43_PHY_AC_TABLE_OFFSET 0x00e
13 #define B43_PHY_AC_TABLE_DATA1 0x00f
14 #define B43_PHY_AC_TABLE_DATA2 0x010
15 #define B43_PHY_AC_TABLE_DATA3 0x011
16 #define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */
[all …]

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