1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2020 Compass Electronics Group, LLC 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun leds { 8*4882a593Smuzhiyun compatible = "gpio-leds"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun led0 { 11*4882a593Smuzhiyun label = "gen_led0"; 12*4882a593Smuzhiyun gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; 13*4882a593Smuzhiyun default-state = "off"; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun led1 { 17*4882a593Smuzhiyun label = "gen_led1"; 18*4882a593Smuzhiyun gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; 19*4882a593Smuzhiyun default-state = "off"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun led2 { 23*4882a593Smuzhiyun label = "gen_led2"; 24*4882a593Smuzhiyun gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; 25*4882a593Smuzhiyun default-state = "off"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun led3 { 29*4882a593Smuzhiyun pinctrl-names = "default"; 30*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led3>; 31*4882a593Smuzhiyun label = "heartbeat"; 32*4882a593Smuzhiyun gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 33*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun reg_audio: regulator-audio { 38*4882a593Smuzhiyun compatible = "regulator-fixed"; 39*4882a593Smuzhiyun regulator-name = "3v3_aud"; 40*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 41*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 42*4882a593Smuzhiyun gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; 43*4882a593Smuzhiyun enable-active-high; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun reg_usdhc2_vmmc: regulator-usdhc2 { 47*4882a593Smuzhiyun compatible = "regulator-fixed"; 48*4882a593Smuzhiyun regulator-name = "VSD_3V3"; 49*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 50*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 51*4882a593Smuzhiyun gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 52*4882a593Smuzhiyun enable-active-high; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun sound { 56*4882a593Smuzhiyun compatible = "fsl,imx-audio-wm8962"; 57*4882a593Smuzhiyun model = "wm8962-audio"; 58*4882a593Smuzhiyun audio-cpu = <&sai3>; 59*4882a593Smuzhiyun audio-codec = <&wm8962>; 60*4882a593Smuzhiyun audio-routing = 61*4882a593Smuzhiyun "Headphone Jack", "HPOUTL", 62*4882a593Smuzhiyun "Headphone Jack", "HPOUTR", 63*4882a593Smuzhiyun "Ext Spk", "SPKOUTL", 64*4882a593Smuzhiyun "Ext Spk", "SPKOUTR", 65*4882a593Smuzhiyun "AMIC", "MICBIAS", 66*4882a593Smuzhiyun "IN3R", "AMIC"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&ecspi2 { 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_espi2>; 73*4882a593Smuzhiyun cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 74*4882a593Smuzhiyun status = "okay"; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun eeprom@0 { 77*4882a593Smuzhiyun compatible = "microchip,at25160bn", "atmel,at25"; 78*4882a593Smuzhiyun reg = <0>; 79*4882a593Smuzhiyun spi-max-frequency = <5000000>; 80*4882a593Smuzhiyun spi-cpha; 81*4882a593Smuzhiyun spi-cpol; 82*4882a593Smuzhiyun pagesize = <32>; 83*4882a593Smuzhiyun size = <2048>; 84*4882a593Smuzhiyun address-width = <16>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&i2c2 { 89*4882a593Smuzhiyun clock-frequency = <400000>; 90*4882a593Smuzhiyun pinctrl-names = "default"; 91*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&i2c4 { 96*4882a593Smuzhiyun clock-frequency = <400000>; 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c4>; 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun wm8962: audio-codec@1a { 102*4882a593Smuzhiyun compatible = "wlf,wm8962"; 103*4882a593Smuzhiyun reg = <0x1a>; 104*4882a593Smuzhiyun clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 105*4882a593Smuzhiyun clock-names = "xclk"; 106*4882a593Smuzhiyun DCVDD-supply = <®_audio>; 107*4882a593Smuzhiyun DBVDD-supply = <®_audio>; 108*4882a593Smuzhiyun AVDD-supply = <®_audio>; 109*4882a593Smuzhiyun CPVDD-supply = <®_audio>; 110*4882a593Smuzhiyun MICVDD-supply = <®_audio>; 111*4882a593Smuzhiyun PLLVDD-supply = <®_audio>; 112*4882a593Smuzhiyun SPKVDD1-supply = <®_audio>; 113*4882a593Smuzhiyun SPKVDD2-supply = <®_audio>; 114*4882a593Smuzhiyun gpio-cfg = < 115*4882a593Smuzhiyun 0x0000 /* 0:Default */ 116*4882a593Smuzhiyun 0x0000 /* 1:Default */ 117*4882a593Smuzhiyun 0x0000 /* 2:FN_DMICCLK */ 118*4882a593Smuzhiyun 0x0000 /* 3:Default */ 119*4882a593Smuzhiyun 0x0000 /* 4:FN_DMICCDAT */ 120*4882a593Smuzhiyun 0x0000 /* 5:Default */ 121*4882a593Smuzhiyun >; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun pca6416_0: gpio@20 { 125*4882a593Smuzhiyun compatible = "nxp,pcal6416"; 126*4882a593Smuzhiyun reg = <0x20>; 127*4882a593Smuzhiyun pinctrl-names = "default"; 128*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcal6414>; 129*4882a593Smuzhiyun gpio-controller; 130*4882a593Smuzhiyun #gpio-cells = <2>; 131*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 132*4882a593Smuzhiyun interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun pca6416_1: gpio@21 { 136*4882a593Smuzhiyun compatible = "nxp,pcal6416"; 137*4882a593Smuzhiyun reg = <0x21>; 138*4882a593Smuzhiyun gpio-controller; 139*4882a593Smuzhiyun #gpio-cells = <2>; 140*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 141*4882a593Smuzhiyun interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&sai3 { 146*4882a593Smuzhiyun pinctrl-names = "default"; 147*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sai3>; 148*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 149*4882a593Smuzhiyun assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 150*4882a593Smuzhiyun assigned-clock-rates = <24576000>; 151*4882a593Smuzhiyun fsl,sai-mclk-direction-output; 152*4882a593Smuzhiyun status = "okay"; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun&snvs_pwrkey { 156*4882a593Smuzhiyun status = "okay"; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun&uart2 { /* console */ 160*4882a593Smuzhiyun pinctrl-names = "default"; 161*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun}; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun&uart3 { 166*4882a593Smuzhiyun pinctrl-names = "default"; 167*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 168*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MM_CLK_UART3>; 169*4882a593Smuzhiyun assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 170*4882a593Smuzhiyun uart-has-rtscts; 171*4882a593Smuzhiyun status = "okay"; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&usdhc2 { 175*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 176*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 177*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 178*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 179*4882a593Smuzhiyun bus-width = <4>; 180*4882a593Smuzhiyun vmmc-supply = <®_usdhc2_vmmc>; 181*4882a593Smuzhiyun status = "okay"; 182*4882a593Smuzhiyun}; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun&iomuxc { 185*4882a593Smuzhiyun pinctrl_espi2: espi2grp { 186*4882a593Smuzhiyun fsl,pins = < 187*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 188*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 189*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 190*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 191*4882a593Smuzhiyun >; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 195*4882a593Smuzhiyun fsl,pins = < 196*4882a593Smuzhiyun MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 197*4882a593Smuzhiyun MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 198*4882a593Smuzhiyun >; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun pinctrl_i2c4: i2c4grp { 202*4882a593Smuzhiyun fsl,pins = < 203*4882a593Smuzhiyun MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 204*4882a593Smuzhiyun MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 205*4882a593Smuzhiyun >; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun pinctrl_led3: led3grp { 209*4882a593Smuzhiyun fsl,pins = < 210*4882a593Smuzhiyun MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 211*4882a593Smuzhiyun >; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun pinctrl_pcal6414: pcal6414-gpiogrp { 215*4882a593Smuzhiyun fsl,pins = < 216*4882a593Smuzhiyun MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 217*4882a593Smuzhiyun >; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun pinctrl_sai3: sai3grp { 221*4882a593Smuzhiyun fsl,pins = < 222*4882a593Smuzhiyun MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 223*4882a593Smuzhiyun MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 224*4882a593Smuzhiyun MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 225*4882a593Smuzhiyun MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 226*4882a593Smuzhiyun MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 227*4882a593Smuzhiyun >; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 231*4882a593Smuzhiyun fsl,pins = < 232*4882a593Smuzhiyun MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 233*4882a593Smuzhiyun MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 234*4882a593Smuzhiyun >; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 238*4882a593Smuzhiyun fsl,pins = < 239*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 240*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 241*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 242*4882a593Smuzhiyun MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 243*4882a593Smuzhiyun >; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun pinctrl_usdhc2_gpio: usdhc2gpiogrp { 247*4882a593Smuzhiyun fsl,pins = < 248*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 249*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 250*4882a593Smuzhiyun >; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 254*4882a593Smuzhiyun fsl,pins = < 255*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 256*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 257*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 258*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 259*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 260*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 261*4882a593Smuzhiyun MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 262*4882a593Smuzhiyun >; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 266*4882a593Smuzhiyun fsl,pins = < 267*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 268*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 269*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 270*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 271*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 272*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 273*4882a593Smuzhiyun MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 274*4882a593Smuzhiyun >; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 278*4882a593Smuzhiyun fsl,pins = < 279*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 280*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 281*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 282*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 283*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 284*4882a593Smuzhiyun MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 285*4882a593Smuzhiyun MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 286*4882a593Smuzhiyun >; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun}; 289