1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2002 MontaVista Software Inc. 6*4882a593Smuzhiyun * Author: Yoichi Yuasa <source@mvista.com> 7*4882a593Smuzhiyun * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __PCI_VR41XX_H 10*4882a593Smuzhiyun #define __PCI_VR41XX_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define PCIU_BASE 0x0f000c00UL 13*4882a593Smuzhiyun #define PCIU_SIZE 0x200UL 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PCIMMAW1REG 0x00 16*4882a593Smuzhiyun #define PCIMMAW2REG 0x04 17*4882a593Smuzhiyun #define PCITAW1REG 0x08 18*4882a593Smuzhiyun #define PCITAW2REG 0x0c 19*4882a593Smuzhiyun #define PCIMIOAWREG 0x10 20*4882a593Smuzhiyun #define IBA(addr) ((addr) & 0xff000000U) 21*4882a593Smuzhiyun #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U) 22*4882a593Smuzhiyun #define PCIA(addr) (((addr) >> 24) & 0x000000ffU) 23*4882a593Smuzhiyun #define TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U) 24*4882a593Smuzhiyun #define ITA(addr) (((addr) >> 24) & 0x000000ffU) 25*4882a593Smuzhiyun #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU) 26*4882a593Smuzhiyun #define WINEN 0x1000U 27*4882a593Smuzhiyun #define PCICONFDREG 0x14 28*4882a593Smuzhiyun #define PCICONFAREG 0x18 29*4882a593Smuzhiyun #define PCIMAILREG 0x1c 30*4882a593Smuzhiyun #define BUSERRADREG 0x24 31*4882a593Smuzhiyun #define EA(reg) ((reg) &0xfffffffc) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define INTCNTSTAREG 0x28 34*4882a593Smuzhiyun #define MABTCLR 0x80000000U 35*4882a593Smuzhiyun #define TRDYCLR 0x40000000U 36*4882a593Smuzhiyun #define PARCLR 0x20000000U 37*4882a593Smuzhiyun #define MBCLR 0x10000000U 38*4882a593Smuzhiyun #define SERRCLR 0x08000000U 39*4882a593Smuzhiyun #define RTYCLR 0x04000000U 40*4882a593Smuzhiyun #define MABCLR 0x02000000U 41*4882a593Smuzhiyun #define TABCLR 0x01000000U 42*4882a593Smuzhiyun /* RFU */ 43*4882a593Smuzhiyun #define MABTMSK 0x00008000U 44*4882a593Smuzhiyun #define TRDYMSK 0x00004000U 45*4882a593Smuzhiyun #define PARMSK 0x00002000U 46*4882a593Smuzhiyun #define MBMSK 0x00001000U 47*4882a593Smuzhiyun #define SERRMSK 0x00000800U 48*4882a593Smuzhiyun #define RTYMSK 0x00000400U 49*4882a593Smuzhiyun #define MABMSK 0x00000200U 50*4882a593Smuzhiyun #define TABMSK 0x00000100U 51*4882a593Smuzhiyun #define IBAMABT 0x00000080U 52*4882a593Smuzhiyun #define TRDYRCH 0x00000040U 53*4882a593Smuzhiyun #define PAR 0x00000020U 54*4882a593Smuzhiyun #define MB 0x00000010U 55*4882a593Smuzhiyun #define PCISERR 0x00000008U 56*4882a593Smuzhiyun #define RTYRCH 0x00000004U 57*4882a593Smuzhiyun #define MABORT 0x00000002U 58*4882a593Smuzhiyun #define TABORT 0x00000001U 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define PCIEXACCREG 0x2c 61*4882a593Smuzhiyun #define UNLOCK 0x2U 62*4882a593Smuzhiyun #define EAREQ 0x1U 63*4882a593Smuzhiyun #define PCIRECONTREG 0x30 64*4882a593Smuzhiyun #define RTRYCNT(reg) ((reg) & 0x000000ffU) 65*4882a593Smuzhiyun #define PCIENREG 0x34 66*4882a593Smuzhiyun #define PCIU_CONFIG_DONE 0x4U 67*4882a593Smuzhiyun #define PCICLKSELREG 0x38 68*4882a593Smuzhiyun #define EQUAL_VTCLOCK 0x2U 69*4882a593Smuzhiyun #define HALF_VTCLOCK 0x0U 70*4882a593Smuzhiyun #define ONE_THIRD_VTCLOCK 0x3U 71*4882a593Smuzhiyun #define QUARTER_VTCLOCK 0x1U 72*4882a593Smuzhiyun #define PCITRDYVREG 0x3c 73*4882a593Smuzhiyun #define TRDYV(val) ((uint32_t)(val) & 0xffU) 74*4882a593Smuzhiyun #define PCICLKRUNREG 0x60 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define VENDORIDREG 0x100 77*4882a593Smuzhiyun #define DEVICEIDREG 0x100 78*4882a593Smuzhiyun #define COMMANDREG 0x104 79*4882a593Smuzhiyun #define STATUSREG 0x104 80*4882a593Smuzhiyun #define REVIDREG 0x108 81*4882a593Smuzhiyun #define CLASSREG 0x108 82*4882a593Smuzhiyun #define CACHELSREG 0x10c 83*4882a593Smuzhiyun #define LATTIMEREG 0x10c 84*4882a593Smuzhiyun #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U) 85*4882a593Smuzhiyun #define MAILBAREG 0x110 86*4882a593Smuzhiyun #define PCIMBA1REG 0x114 87*4882a593Smuzhiyun #define PCIMBA2REG 0x118 88*4882a593Smuzhiyun #define MBADD(base) ((base) & 0xfffff800U) 89*4882a593Smuzhiyun #define PMBA(base) ((base) & 0xffe00000U) 90*4882a593Smuzhiyun #define PREF 0x8U 91*4882a593Smuzhiyun #define PREF_APPROVAL 0x8U 92*4882a593Smuzhiyun #define PREF_DISAPPROVAL 0x0U 93*4882a593Smuzhiyun #define TYPE 0x6U 94*4882a593Smuzhiyun #define TYPE_32BITSPACE 0x0U 95*4882a593Smuzhiyun #define MSI 0x1U 96*4882a593Smuzhiyun #define MSI_MEMORY 0x0U 97*4882a593Smuzhiyun #define INTLINEREG 0x13c 98*4882a593Smuzhiyun #define INTPINREG 0x13c 99*4882a593Smuzhiyun #define RETVALREG 0x140 100*4882a593Smuzhiyun #define PCIAPCNTREG 0x140 101*4882a593Smuzhiyun #define TKYGNT 0x04000000U 102*4882a593Smuzhiyun #define TKYGNT_ENABLE 0x04000000U 103*4882a593Smuzhiyun #define TKYGNT_DISABLE 0x00000000U 104*4882a593Smuzhiyun #define PAPC 0x03000000U 105*4882a593Smuzhiyun #define PAPC_ALTERNATE_B 0x02000000U 106*4882a593Smuzhiyun #define PAPC_ALTERNATE_0 0x01000000U 107*4882a593Smuzhiyun #define PAPC_FAIR 0x00000000U 108*4882a593Smuzhiyun #define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U) 109*4882a593Smuzhiyun #define RTYVAL_MASK 0xff00U 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define PCI_CLOCK_MAX 33333333U 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Default setup 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun #define PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U 117*4882a593Smuzhiyun #define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U 118*4882a593Smuzhiyun #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U 121*4882a593Smuzhiyun #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U 124*4882a593Smuzhiyun #define PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U 125*4882a593Smuzhiyun #define PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define PCI_MAILBOX_BASE_ADDRESS 0x00000000U 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS) 132*4882a593Smuzhiyun #define IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS 133*4882a593Smuzhiyun #define IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define PCI_IO_RESOURCE_START 0x01000000UL 136*4882a593Smuzhiyun #define PCI_IO_RESOURCE_END 0x01ffffffUL 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define PCI_MEM_RESOURCE_START 0x11000000UL 139*4882a593Smuzhiyun #define PCI_MEM_RESOURCE_END 0x13ffffffUL 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* __PCI_VR41XX_H */ 142