Lines Matching +full:0 +full:x140
21 pinctrl-0 = <&pinctrl_gpio_led>;
32 reg = <0x0 0x40000000 0 0xc0000000>,
33 <0x1 0x00000000 0 0xc0000000>;
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
50 pinctrl-0 = <&pinctrl_fec>;
58 #size-cells = <0>;
74 pinctrl-0 = <&pinctrl_i2c3>;
79 reg = <0x20>;
92 pinctrl-0 = <&pinctrl_uart2>;
100 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
113 pinctrl-0 = <&pinctrl_usdhc3>;
123 pinctrl-0 = <&pinctrl_wdog>;
131 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
132 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
133 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
134 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
135 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
136 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
137 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
138 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
139 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
140 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
141 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
142 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
143 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
144 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
145 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
151 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
157 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
158 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
164 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
170 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
171 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
177 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
178 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
179 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
180 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
181 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
182 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
183 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
189 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
190 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
191 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
192 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
193 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
194 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
195 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
201 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
202 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
203 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
204 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
205 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
206 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
207 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
213 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
219 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
220 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
221 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
222 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
223 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
224 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
225 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
226 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
227 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
228 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
229 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
235 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
236 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
237 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
238 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
239 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
240 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
241 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
242 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
243 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
244 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
245 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
251 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
252 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
253 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
254 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
255 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
256 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
257 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
258 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
259 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
260 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
261 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
267 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6