1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef B43_PHY_AC_H_ 3*4882a593Smuzhiyun #define B43_PHY_AC_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include "phy_common.h" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define B43_PHY_AC_BBCFG 0x001 8*4882a593Smuzhiyun #define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */ 9*4882a593Smuzhiyun #define B43_PHY_AC_BANDCTL 0x003 /* Band control */ 10*4882a593Smuzhiyun #define B43_PHY_AC_BANDCTL_5GHZ 0x0001 11*4882a593Smuzhiyun #define B43_PHY_AC_TABLE_ID 0x00d 12*4882a593Smuzhiyun #define B43_PHY_AC_TABLE_OFFSET 0x00e 13*4882a593Smuzhiyun #define B43_PHY_AC_TABLE_DATA1 0x00f 14*4882a593Smuzhiyun #define B43_PHY_AC_TABLE_DATA2 0x010 15*4882a593Smuzhiyun #define B43_PHY_AC_TABLE_DATA3 0x011 16*4882a593Smuzhiyun #define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */ 17*4882a593Smuzhiyun #define B43_PHY_AC_CLASSCTL_CCKEN 0x0001 /* CCK enable */ 18*4882a593Smuzhiyun #define B43_PHY_AC_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */ 19*4882a593Smuzhiyun #define B43_PHY_AC_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */ 20*4882a593Smuzhiyun #define B43_PHY_AC_BW1A 0x371 21*4882a593Smuzhiyun #define B43_PHY_AC_BW2 0x372 22*4882a593Smuzhiyun #define B43_PHY_AC_BW3 0x373 23*4882a593Smuzhiyun #define B43_PHY_AC_BW4 0x374 24*4882a593Smuzhiyun #define B43_PHY_AC_BW5 0x375 25*4882a593Smuzhiyun #define B43_PHY_AC_BW6 0x376 26*4882a593Smuzhiyun #define B43_PHY_AC_RFCTL_CMD 0x408 27*4882a593Smuzhiyun #define B43_PHY_AC_C1_CLIP 0x6d4 28*4882a593Smuzhiyun #define B43_PHY_AC_C1_CLIP_DIS 0x4000 29*4882a593Smuzhiyun #define B43_PHY_AC_C2_CLIP 0x8d4 30*4882a593Smuzhiyun #define B43_PHY_AC_C2_CLIP_DIS 0x4000 31*4882a593Smuzhiyun #define B43_PHY_AC_C3_CLIP 0xad4 32*4882a593Smuzhiyun #define B43_PHY_AC_C3_CLIP_DIS 0x4000 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct b43_phy_ac { 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun extern const struct b43_phy_operations b43_phyops_ac; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* B43_PHY_AC_H_ */ 40