Lines Matching +full:0 +full:x140
13 /* 0x000 */
19 /* 0x010 */
24 /* 0x020 */
27 /* 0x100 */
34 /* 0x120 */
40 /* 0x130 */
43 /* 0x140 */
49 /* 0x150 */
55 /* 0x160 */
61 /* 0x170 */
67 /* 0x180 */
72 /* 0x1a0 */
78 /* 0x1b0 */
81 /* 0x200 */
82 uint reserved11[0x80];
84 /* 0x130 */
90 /* 0x140 */
96 /* 0x150 */
102 /* 0x160 */
106 /* 0x170 */
111 /* 0x190 */
114 /* 0x1b0 */
119 /* 0x1c0 */
122 /* 0x1d0 */
125 /* 0x1e0 */
128 /* 0x1f0 */
134 /* 0x200 */
138 uint reserved11_1[0x7D];
141 /* 0x400 */
148 /* 0x410 */
152 /* 0x424 */
158 /* 0x410 */
162 /* 0x420 */
166 /* 0x500 */
169 /* 0x800 */
175 /* 0x810 */
181 /* 0x820 */
187 /* 0x830 */
199 #define VBUS_SENSE_CTL_VBUS_WAKEUP 0
219 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
220 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
222 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
224 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
239 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
246 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
252 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
253 #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
254 #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
262 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
263 #define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
265 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
271 (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
274 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
277 #define UTMIP_DEBOUNCE_CFG0_SHIFT 0
278 #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
291 #define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
294 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
299 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
317 #define PTS_MASK (0x7U << PTS_SHIFT)
321 #define PTS_UTMI 0
339 (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
341 #define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
342 #define UTMIP_XCVR_SETUP_SHIFT 0
343 #define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
348 (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
349 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)