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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,pericfg.yaml56 reg = <0x10003000 0x1000>;
64 reg = <0x10003000 0x1000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Dfsl,imxgpt.yaml67 reg = <0x10003000 0x1000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml49 minimum: 0
57 minimum: 0
78 reg = <0x10003000 0x40>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
H A Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
76 offset = <0x08>;
77 mask = <0x01>;
78 label = "versatile:0";
[all …]
H A Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
H A Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
/OK3568_Linux_fs/u-boot/arch/mips/dts/
H A Dbrcm,bcm6328.dtsi17 reg = <0x10000000 0x4>;
19 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
45 #clock-cells = <0>;
52 reg = <0x10000004 0x4>;
65 reg = <0x10000010 0x4>;
71 reg = <0x10000068 0x4>;
77 offset = <0x0>;
78 mask = <0x1>;
[all …]
H A Dbrcm,bcm63268.dtsi17 reg = <0x10000000 0x4>;
19 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
45 #clock-cells = <0>;
52 reg = <0x10000004 0x4>;
58 reg = <0x100000ac 0x4>;
71 reg = <0x10000008 0x4>;
77 offset = <0x0>;
78 mask = <0x1>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dinterrupts.txt17 interrupts = <5 0>, <6 0>;
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
55 reg = <0x10140000 0x1000>;
62 reg = <0x10003000 0x1000>;
72 - bits[3:0] trigger type and level flags
83 reg = <0x41>;
99 reg = <0x2b>;
102 interrupts = <3 0x8>;
105 #size-cells = <0>;
107 threshold = <0x40>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dsc9836.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0 0x0>;
29 reg = <0x0 0x1>;
36 reg = <0x0 0x2>;
43 reg = <0x0 0x3>;
50 reg = <0 0x10003000 0 0x1000>;
64 reg = <0 0x10001000 0 0x1000>;
78 #size-cells = <0>;
80 port@0 {
[all …]
H A Dsc9863a.dtsi15 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
57 reg = <0x0 0x100>;
65 reg = <0x0 0x200>;
73 reg = <0x0 0x300>;
81 reg = <0x0 0x400>;
89 reg = <0x0 0x500>;
97 reg = <0x0 0x600>;
105 reg = <0x0 0x700>;
[all …]
H A Dsc9860.dtsi17 #size-cells = <0>;
54 reg = <0x0 0x530000>;
62 reg = <0x0 0x530001>;
70 reg = <0x0 0x530002>;
78 reg = <0x0 0x530003>;
86 reg = <0x0 0x530100>;
94 reg = <0x0 0x530101>;
102 reg = <0x0 0x530102>;
110 reg = <0x0 0x530103>;
125 arm,psci-suspend-param = <0x00010002>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-ralink/
H A Drt3883.h13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx27.c16 #define MX27_CCM_BASE_ADDR 0x10027000
17 #define MX27_GPT1_BASE_ADDR 0x10003000
23 #define CCM_CSCR (ccm + 0x00)
24 #define CCM_MPCTL0 (ccm + 0x04)
25 #define CCM_MPCTL1 (ccm + 0x08)
26 #define CCM_SPCTL0 (ccm + 0x0c)
27 #define CCM_SPCTL1 (ccm + 0x10)
28 #define CCM_PCDR0 (ccm + 0x18)
29 #define CCM_PCDR1 (ccm + 0x1c)
30 #define CCM_PCCR0 (ccm + 0x20)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra186.dtsi19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
36 reg = <0x0 0x02490000 0x0 0x10000>;
56 reg = <0x0 0x03100000 0x0 0x10000>;
63 reg = <0x0 0x3160000 0x0 0x100>;
66 #size-cells = <0>;
76 reg = <0x0 0x3180000 0x0 0x100>;
79 #size-cells = <0>;
89 reg = <0x0 0x3190000 0x0 0x100>;
92 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/sandbox/dts/
H A Dtest.dts14 i2c0 = "/i2c@0";
22 spi0 = "/spi@0";
25 testfdt0 = "/some-bus/c-test@0";
36 reg = <0 1>;
38 ping-expect = <0>;
39 ping-add = <0>;
41 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
42 <0>, <&gpio_a 12>;
45 <&gpio_b 9 0xc 3 2 1>;
64 phy_provider0: gen_phy@0 {
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]

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