xref: /OK3568_Linux_fs/u-boot/arch/mips/dts/brcm,bcm6328.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/clock/bcm6328-clock.h>
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun#include <dt-bindings/power-domain/bcm6328-power-domain.h>
10*4882a593Smuzhiyun#include <dt-bindings/reset/bcm6328-reset.h>
11*4882a593Smuzhiyun#include "skeleton.dtsi"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	compatible = "brcm,bcm6328";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	cpus {
17*4882a593Smuzhiyun		reg = <0x10000000 0x4>;
18*4882a593Smuzhiyun		#address-cells = <1>;
19*4882a593Smuzhiyun		#size-cells = <0>;
20*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun		cpu@0 {
23*4882a593Smuzhiyun			compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
24*4882a593Smuzhiyun			device_type = "cpu";
25*4882a593Smuzhiyun			reg = <0>;
26*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		cpu@1 {
30*4882a593Smuzhiyun			compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
31*4882a593Smuzhiyun			device_type = "cpu";
32*4882a593Smuzhiyun			reg = <1>;
33*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	clocks {
38*4882a593Smuzhiyun		compatible = "simple-bus";
39*4882a593Smuzhiyun		#address-cells = <1>;
40*4882a593Smuzhiyun		#size-cells = <1>;
41*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		periph_osc: periph-osc {
44*4882a593Smuzhiyun			compatible = "fixed-clock";
45*4882a593Smuzhiyun			#clock-cells = <0>;
46*4882a593Smuzhiyun			clock-frequency = <50000000>;
47*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		periph_clk: periph-clk {
51*4882a593Smuzhiyun			compatible = "brcm,bcm6345-clk";
52*4882a593Smuzhiyun			reg = <0x10000004 0x4>;
53*4882a593Smuzhiyun			#clock-cells = <1>;
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	ubus {
58*4882a593Smuzhiyun		compatible = "simple-bus";
59*4882a593Smuzhiyun		#address-cells = <1>;
60*4882a593Smuzhiyun		#size-cells = <1>;
61*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		periph_rst: reset-controller@10000010 {
64*4882a593Smuzhiyun			compatible = "brcm,bcm6345-reset";
65*4882a593Smuzhiyun			reg = <0x10000010 0x4>;
66*4882a593Smuzhiyun			#reset-cells = <1>;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		pll_cntl: syscon@10000068 {
70*4882a593Smuzhiyun			compatible = "syscon";
71*4882a593Smuzhiyun			reg = <0x10000068 0x4>;
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		syscon-reboot {
75*4882a593Smuzhiyun			compatible = "syscon-reboot";
76*4882a593Smuzhiyun			regmap = <&pll_cntl>;
77*4882a593Smuzhiyun			offset = <0x0>;
78*4882a593Smuzhiyun			mask = <0x1>;
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		wdt: watchdog@1000005c {
82*4882a593Smuzhiyun			compatible = "brcm,bcm6345-wdt";
83*4882a593Smuzhiyun			reg = <0x1000005c 0xc>;
84*4882a593Smuzhiyun			clocks = <&periph_osc>;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		wdt-reboot {
88*4882a593Smuzhiyun			compatible = "wdt-reboot";
89*4882a593Smuzhiyun			wdt = <&wdt>;
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		gpio: gpio-controller@10000084 {
93*4882a593Smuzhiyun			compatible = "brcm,bcm6345-gpio";
94*4882a593Smuzhiyun			reg = <0x10000084 0x4>, <0x1000008c 0x4>;
95*4882a593Smuzhiyun			gpio-controller;
96*4882a593Smuzhiyun			#gpio-cells = <2>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun			status = "disabled";
99*4882a593Smuzhiyun		};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun		uart0: serial@10000100 {
102*4882a593Smuzhiyun			compatible = "brcm,bcm6345-uart";
103*4882a593Smuzhiyun			reg = <0x10000100 0x18>;
104*4882a593Smuzhiyun			clocks = <&periph_osc>;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun			status = "disabled";
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun		uart1: serial@10000120 {
110*4882a593Smuzhiyun			compatible = "brcm,bcm6345-uart";
111*4882a593Smuzhiyun			reg = <0x10000120 0x18>;
112*4882a593Smuzhiyun			clocks = <&periph_osc>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun			status = "disabled";
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		leds: led-controller@10000800 {
118*4882a593Smuzhiyun			compatible = "brcm,bcm6328-leds";
119*4882a593Smuzhiyun			reg = <0x10000800 0x24>;
120*4882a593Smuzhiyun			#address-cells = <1>;
121*4882a593Smuzhiyun			#size-cells = <0>;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun			status = "disabled";
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		periph_pwr: power-controller@10001848 {
127*4882a593Smuzhiyun			compatible = "brcm,bcm6328-power-domain";
128*4882a593Smuzhiyun			reg = <0x10001848 0x4>;
129*4882a593Smuzhiyun			#power-domain-cells = <1>;
130*4882a593Smuzhiyun		};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun		memory-controller@10003000 {
133*4882a593Smuzhiyun			compatible = "brcm,bcm6328-mc";
134*4882a593Smuzhiyun			reg = <0x10003000 0x864>;
135*4882a593Smuzhiyun			u-boot,dm-pre-reloc;
136*4882a593Smuzhiyun		};
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun};
139