1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Hisilicon Ltd. HiP01 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014 Hisilicon Ltd. 6*4882a593Smuzhiyun * Copyright (c) 2014 Huawei Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Wang Long <long.wanglong@huawei.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun interrupt-parent = <&gic>; 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <1>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun gic: interrupt-controller@1e001000 { 17*4882a593Smuzhiyun compatible = "arm,cortex-a9-gic"; 18*4882a593Smuzhiyun #interrupt-cells = <3>; 19*4882a593Smuzhiyun #address-cells = <0>; 20*4882a593Smuzhiyun interrupt-controller; 21*4882a593Smuzhiyun reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun hisi_refclk144mhz: refclk144mkhz { 25*4882a593Smuzhiyun compatible = "fixed-clock"; 26*4882a593Smuzhiyun #clock-cells = <0>; 27*4882a593Smuzhiyun clock-frequency = <144000000>; 28*4882a593Smuzhiyun clock-output-names = "hisi:refclk144khz"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun soc { 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <1>; 34*4882a593Smuzhiyun compatible = "simple-bus"; 35*4882a593Smuzhiyun interrupt-parent = <&gic>; 36*4882a593Smuzhiyun ranges = <0 0x10000000 0x20000000>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun amba { 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <1>; 41*4882a593Smuzhiyun compatible = "simple-bus"; 42*4882a593Smuzhiyun ranges; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun uart0: uart@10001000 { 45*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 46*4882a593Smuzhiyun reg = <0x10001000 0x1000>; 47*4882a593Smuzhiyun clocks = <&hisi_refclk144mhz>; 48*4882a593Smuzhiyun clock-names = "apb_pclk"; 49*4882a593Smuzhiyun reg-shift = <2>; 50*4882a593Smuzhiyun interrupts = <0 32 4>; 51*4882a593Smuzhiyun status = "disabled"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun uart1: uart@10002000 { 55*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 56*4882a593Smuzhiyun reg = <0x10002000 0x1000>; 57*4882a593Smuzhiyun clocks = <&hisi_refclk144mhz>; 58*4882a593Smuzhiyun clock-names = "apb_pclk"; 59*4882a593Smuzhiyun reg-shift = <2>; 60*4882a593Smuzhiyun interrupts = <0 33 4>; 61*4882a593Smuzhiyun status = "disabled"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun uart2: uart@10003000 { 65*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 66*4882a593Smuzhiyun reg = <0x10003000 0x1000>; 67*4882a593Smuzhiyun clocks = <&hisi_refclk144mhz>; 68*4882a593Smuzhiyun clock-names = "apb_pclk"; 69*4882a593Smuzhiyun reg-shift = <2>; 70*4882a593Smuzhiyun interrupts = <0 34 4>; 71*4882a593Smuzhiyun status = "disabled"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun uart3: uart@10006000 { 75*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 76*4882a593Smuzhiyun reg = <0x10006000 0x1000>; 77*4882a593Smuzhiyun clocks = <&hisi_refclk144mhz>; 78*4882a593Smuzhiyun clock-names = "apb_pclk"; 79*4882a593Smuzhiyun reg-shift = <2>; 80*4882a593Smuzhiyun interrupts = <0 4 4>; 81*4882a593Smuzhiyun status = "disabled"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun system-controller@10000000 { 86*4882a593Smuzhiyun compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; 87*4882a593Smuzhiyun reg = <0x10000000 0x1000>; 88*4882a593Smuzhiyun reboot-offset = <0x4>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun global_timer@a000200 { 92*4882a593Smuzhiyun compatible = "arm,cortex-a9-global-timer"; 93*4882a593Smuzhiyun reg = <0x0a000200 0x100>; 94*4882a593Smuzhiyun interrupts = <1 11 0xf04>; 95*4882a593Smuzhiyun clocks = <&hisi_refclk144mhz>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun local_timer@a000600 { 99*4882a593Smuzhiyun compatible = "arm,cortex-a9-twd-timer"; 100*4882a593Smuzhiyun reg = <0x0a000600 0x100>; 101*4882a593Smuzhiyun interrupts = <1 13 0xf04>; 102*4882a593Smuzhiyun clocks = <&hisi_refclk144mhz>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun}; 106