xref: /OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/jz4770.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun#include <dt-bindings/clock/jz4770-cgu.h>
3*4882a593Smuzhiyun#include <dt-bindings/clock/ingenic,tcu.h>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	#address-cells = <1>;
7*4882a593Smuzhiyun	#size-cells = <1>;
8*4882a593Smuzhiyun	compatible = "ingenic,jz4770";
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	cpus {
11*4882a593Smuzhiyun		#address-cells = <1>;
12*4882a593Smuzhiyun		#size-cells = <0>;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun		cpu0: cpu@0 {
15*4882a593Smuzhiyun			device_type = "cpu";
16*4882a593Smuzhiyun			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17*4882a593Smuzhiyun			reg = <0>;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun			clocks = <&cgu JZ4770_CLK_CCLK>;
20*4882a593Smuzhiyun			clock-names = "cpu";
21*4882a593Smuzhiyun		};
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	cpuintc: interrupt-controller {
25*4882a593Smuzhiyun		#address-cells = <0>;
26*4882a593Smuzhiyun		#interrupt-cells = <1>;
27*4882a593Smuzhiyun		interrupt-controller;
28*4882a593Smuzhiyun		compatible = "mti,cpu-interrupt-controller";
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	intc: interrupt-controller@10001000 {
32*4882a593Smuzhiyun		compatible = "ingenic,jz4770-intc";
33*4882a593Smuzhiyun		reg = <0x10001000 0x40>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		interrupt-controller;
36*4882a593Smuzhiyun		#interrupt-cells = <1>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		interrupt-parent = <&cpuintc>;
39*4882a593Smuzhiyun		interrupts = <2>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	ext: ext {
43*4882a593Smuzhiyun		compatible = "fixed-clock";
44*4882a593Smuzhiyun		#clock-cells = <0>;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	osc32k: osc32k {
48*4882a593Smuzhiyun		compatible = "fixed-clock";
49*4882a593Smuzhiyun		#clock-cells = <0>;
50*4882a593Smuzhiyun		clock-frequency = <32768>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	cgu: jz4770-cgu@10000000 {
54*4882a593Smuzhiyun		compatible = "ingenic,jz4770-cgu", "simple-mfd";
55*4882a593Smuzhiyun		reg = <0x10000000 0x100>;
56*4882a593Smuzhiyun		#address-cells = <1>;
57*4882a593Smuzhiyun		#size-cells = <1>;
58*4882a593Smuzhiyun		ranges = <0x0 0x10000000 0x100>;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		clocks = <&ext>, <&osc32k>;
61*4882a593Smuzhiyun		clock-names = "ext", "osc32k";
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		#clock-cells = <1>;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		otg_phy: usb-phy@3c {
66*4882a593Smuzhiyun			compatible = "ingenic,jz4770-phy";
67*4882a593Smuzhiyun			reg = <0x3c 0x10>;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun			clocks = <&cgu JZ4770_CLK_OTG_PHY>;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun			#phy-cells = <0>;
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	tcu: timer@10002000 {
76*4882a593Smuzhiyun		compatible = "ingenic,jz4770-tcu", "simple-mfd";
77*4882a593Smuzhiyun		reg = <0x10002000 0x1000>;
78*4882a593Smuzhiyun		#address-cells = <1>;
79*4882a593Smuzhiyun		#size-cells = <1>;
80*4882a593Smuzhiyun		ranges = <0x0 0x10002000 0x1000>;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun		#clock-cells = <1>;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_RTC>,
85*4882a593Smuzhiyun			 <&cgu JZ4770_CLK_EXT>,
86*4882a593Smuzhiyun			 <&cgu JZ4770_CLK_PCLK>;
87*4882a593Smuzhiyun		clock-names = "rtc", "ext", "pclk";
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		interrupt-controller;
90*4882a593Smuzhiyun		#interrupt-cells = <1>;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		interrupt-parent = <&intc>;
93*4882a593Smuzhiyun		interrupts = <27 26 25>;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun		watchdog: watchdog@0 {
96*4882a593Smuzhiyun			compatible = "ingenic,jz4770-watchdog",
97*4882a593Smuzhiyun				     "ingenic,jz4740-watchdog";
98*4882a593Smuzhiyun			reg = <0x0 0xc>;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun			clocks = <&tcu TCU_CLK_WDT>;
101*4882a593Smuzhiyun			clock-names = "wdt";
102*4882a593Smuzhiyun		};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun		pwm: pwm@40 {
105*4882a593Smuzhiyun			compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm";
106*4882a593Smuzhiyun			reg = <0x40 0x80>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun			#pwm-cells = <3>;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun			clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
111*4882a593Smuzhiyun				 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
112*4882a593Smuzhiyun				 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
113*4882a593Smuzhiyun				 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
114*4882a593Smuzhiyun			clock-names = "timer0", "timer1", "timer2", "timer3",
115*4882a593Smuzhiyun				      "timer4", "timer5", "timer6", "timer7";
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun		ost: timer@e0 {
119*4882a593Smuzhiyun			compatible = "ingenic,jz4770-ost";
120*4882a593Smuzhiyun			reg = <0xe0 0x20>;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun			clocks = <&tcu TCU_CLK_OST>;
123*4882a593Smuzhiyun			clock-names = "ost";
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun			interrupts = <15>;
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	rtc: rtc@10003000 {
130*4882a593Smuzhiyun		compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc";
131*4882a593Smuzhiyun		reg = <0x10003000 0x40>;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun		interrupt-parent = <&intc>;
134*4882a593Smuzhiyun		interrupts = <32>;
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	pinctrl: pin-controller@10010000 {
138*4882a593Smuzhiyun		compatible = "ingenic,jz4770-pinctrl";
139*4882a593Smuzhiyun		reg = <0x10010000 0x600>;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		#address-cells = <1>;
142*4882a593Smuzhiyun		#size-cells = <0>;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun		gpa: gpio@0 {
145*4882a593Smuzhiyun			compatible = "ingenic,jz4770-gpio";
146*4882a593Smuzhiyun			reg = <0>;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun			gpio-controller;
149*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 0 32>;
150*4882a593Smuzhiyun			#gpio-cells = <2>;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun			interrupt-controller;
153*4882a593Smuzhiyun			#interrupt-cells = <2>;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun			interrupt-parent = <&intc>;
156*4882a593Smuzhiyun			interrupts = <17>;
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun		gpb: gpio@1 {
160*4882a593Smuzhiyun			compatible = "ingenic,jz4770-gpio";
161*4882a593Smuzhiyun			reg = <1>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			gpio-controller;
164*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 32 32>;
165*4882a593Smuzhiyun			#gpio-cells = <2>;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun			interrupt-controller;
168*4882a593Smuzhiyun			#interrupt-cells = <2>;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun			interrupt-parent = <&intc>;
171*4882a593Smuzhiyun			interrupts = <16>;
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun		gpc: gpio@2 {
175*4882a593Smuzhiyun			compatible = "ingenic,jz4770-gpio";
176*4882a593Smuzhiyun			reg = <2>;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun			gpio-controller;
179*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 64 32>;
180*4882a593Smuzhiyun			#gpio-cells = <2>;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun			interrupt-controller;
183*4882a593Smuzhiyun			#interrupt-cells = <2>;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun			interrupt-parent = <&intc>;
186*4882a593Smuzhiyun			interrupts = <15>;
187*4882a593Smuzhiyun		};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun		gpd: gpio@3 {
190*4882a593Smuzhiyun			compatible = "ingenic,jz4770-gpio";
191*4882a593Smuzhiyun			reg = <3>;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun			gpio-controller;
194*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 96 32>;
195*4882a593Smuzhiyun			#gpio-cells = <2>;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun			interrupt-controller;
198*4882a593Smuzhiyun			#interrupt-cells = <2>;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun			interrupt-parent = <&intc>;
201*4882a593Smuzhiyun			interrupts = <14>;
202*4882a593Smuzhiyun		};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun		gpe: gpio@4 {
205*4882a593Smuzhiyun			compatible = "ingenic,jz4770-gpio";
206*4882a593Smuzhiyun			reg = <4>;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun			gpio-controller;
209*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 128 32>;
210*4882a593Smuzhiyun			#gpio-cells = <2>;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun			interrupt-controller;
213*4882a593Smuzhiyun			#interrupt-cells = <2>;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun			interrupt-parent = <&intc>;
216*4882a593Smuzhiyun			interrupts = <13>;
217*4882a593Smuzhiyun		};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun		gpf: gpio@5 {
220*4882a593Smuzhiyun			compatible = "ingenic,jz4770-gpio";
221*4882a593Smuzhiyun			reg = <5>;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			gpio-controller;
224*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 160 32>;
225*4882a593Smuzhiyun			#gpio-cells = <2>;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun			interrupt-controller;
228*4882a593Smuzhiyun			#interrupt-cells = <2>;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun			interrupt-parent = <&intc>;
231*4882a593Smuzhiyun			interrupts = <12>;
232*4882a593Smuzhiyun		};
233*4882a593Smuzhiyun	};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun	aic: audio-controller@10020000 {
236*4882a593Smuzhiyun		compatible = "ingenic,jz4770-i2s";
237*4882a593Smuzhiyun		reg = <0x10020000 0x94>;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun		#sound-dai-cells = <0>;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
242*4882a593Smuzhiyun			 <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
243*4882a593Smuzhiyun		clock-names = "aic", "i2s", "ext", "pll half";
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun		interrupt-parent = <&intc>;
246*4882a593Smuzhiyun		interrupts = <34>;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun		dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>;
249*4882a593Smuzhiyun		dma-names = "rx", "tx";
250*4882a593Smuzhiyun	};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun	codec: audio-codec@100200a0 {
253*4882a593Smuzhiyun		compatible = "ingenic,jz4770-codec";
254*4882a593Smuzhiyun		reg = <0x100200a4 0x8>;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun		#sound-dai-cells = <0>;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_AIC>;
259*4882a593Smuzhiyun		clock-names = "aic";
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	mmc0: mmc@10021000 {
263*4882a593Smuzhiyun		compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
264*4882a593Smuzhiyun		reg = <0x10021000 0x1000>;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_MMC0>;
267*4882a593Smuzhiyun		clock-names = "mmc";
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun		interrupt-parent = <&intc>;
270*4882a593Smuzhiyun		interrupts = <37>;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun		dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>;
273*4882a593Smuzhiyun		dma-names = "rx", "tx";
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun		cap-sd-highspeed;
276*4882a593Smuzhiyun		cap-mmc-highspeed;
277*4882a593Smuzhiyun		cap-sdio-irq;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun		status = "disabled";
280*4882a593Smuzhiyun	};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	mmc1: mmc@10022000 {
283*4882a593Smuzhiyun		compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
284*4882a593Smuzhiyun		reg = <0x10022000 0x1000>;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_MMC1>;
287*4882a593Smuzhiyun		clock-names = "mmc";
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun		interrupt-parent = <&intc>;
290*4882a593Smuzhiyun		interrupts = <36>;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun		dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>;
293*4882a593Smuzhiyun		dma-names = "rx", "tx";
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun		cap-sd-highspeed;
296*4882a593Smuzhiyun		cap-mmc-highspeed;
297*4882a593Smuzhiyun		cap-sdio-irq;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun		status = "disabled";
300*4882a593Smuzhiyun	};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun	mmc2: mmc@10023000 {
303*4882a593Smuzhiyun		compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
304*4882a593Smuzhiyun		reg = <0x10023000 0x1000>;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_MMC2>;
307*4882a593Smuzhiyun		clock-names = "mmc";
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun		interrupt-parent = <&intc>;
310*4882a593Smuzhiyun		interrupts = <35>;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun		dmas = <&dmac1 37 0xffffffff>, <&dmac1 36 0xffffffff>;
313*4882a593Smuzhiyun		dma-names = "rx", "tx";
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun		cap-sd-highspeed;
316*4882a593Smuzhiyun		cap-mmc-highspeed;
317*4882a593Smuzhiyun		cap-sdio-irq;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun		status = "disabled";
320*4882a593Smuzhiyun	};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun	uart0: serial@10030000 {
323*4882a593Smuzhiyun		compatible = "ingenic,jz4770-uart";
324*4882a593Smuzhiyun		reg = <0x10030000 0x100>;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun		clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
327*4882a593Smuzhiyun		clock-names = "baud", "module";
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun		interrupt-parent = <&intc>;
330*4882a593Smuzhiyun		interrupts = <5>;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun		status = "disabled";
333*4882a593Smuzhiyun	};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun	uart1: serial@10031000 {
336*4882a593Smuzhiyun		compatible = "ingenic,jz4770-uart";
337*4882a593Smuzhiyun		reg = <0x10031000 0x100>;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun		clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
340*4882a593Smuzhiyun		clock-names = "baud", "module";
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun		interrupt-parent = <&intc>;
343*4882a593Smuzhiyun		interrupts = <4>;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun		status = "disabled";
346*4882a593Smuzhiyun	};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun	uart2: serial@10032000 {
349*4882a593Smuzhiyun		compatible = "ingenic,jz4770-uart";
350*4882a593Smuzhiyun		reg = <0x10032000 0x100>;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun		clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
353*4882a593Smuzhiyun		clock-names = "baud", "module";
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun		interrupt-parent = <&intc>;
356*4882a593Smuzhiyun		interrupts = <3>;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun		status = "disabled";
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun	uart3: serial@10033000 {
362*4882a593Smuzhiyun		compatible = "ingenic,jz4770-uart";
363*4882a593Smuzhiyun		reg = <0x10033000 0x100>;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun		clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
366*4882a593Smuzhiyun		clock-names = "baud", "module";
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun		interrupt-parent = <&intc>;
369*4882a593Smuzhiyun		interrupts = <2>;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun		status = "disabled";
372*4882a593Smuzhiyun	};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun	adc: adc@10070000 {
375*4882a593Smuzhiyun		compatible = "ingenic,jz4770-adc";
376*4882a593Smuzhiyun		reg = <0x10070000 0x30>;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun		#io-channel-cells = <1>;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_ADC>;
381*4882a593Smuzhiyun		clock-names = "adc";
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun		interrupt-parent = <&intc>;
384*4882a593Smuzhiyun		interrupts = <18>;
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun	gpu: gpu@13040000 {
388*4882a593Smuzhiyun		compatible = "vivante,gc";
389*4882a593Smuzhiyun		reg = <0x13040000 0x10000>;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_GPU>,
392*4882a593Smuzhiyun			 <&cgu JZ4770_CLK_GPU>,
393*4882a593Smuzhiyun			 <&cgu JZ4770_CLK_GPU>;
394*4882a593Smuzhiyun		clock-names = "bus", "core", "shader";
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun		interrupt-parent = <&intc>;
397*4882a593Smuzhiyun		interrupts = <6>;
398*4882a593Smuzhiyun	};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun	lcd: lcd-controller@13050000 {
401*4882a593Smuzhiyun		compatible = "ingenic,jz4770-lcd";
402*4882a593Smuzhiyun		reg = <0x13050000 0x300>;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun		interrupt-parent = <&intc>;
405*4882a593Smuzhiyun		interrupts = <31>;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_LPCLK_MUX>;
408*4882a593Smuzhiyun		clock-names = "lcd_pclk";
409*4882a593Smuzhiyun	};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun	dmac0: dma-controller@13420000 {
412*4882a593Smuzhiyun		compatible = "ingenic,jz4770-dma";
413*4882a593Smuzhiyun		reg = <0x13420000 0xC0>, <0x13420300 0x20>;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun		#dma-cells = <2>;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_DMA>;
418*4882a593Smuzhiyun		interrupt-parent = <&intc>;
419*4882a593Smuzhiyun		interrupts = <24>;
420*4882a593Smuzhiyun	};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun	dmac1: dma-controller@13420100 {
423*4882a593Smuzhiyun		compatible = "ingenic,jz4770-dma";
424*4882a593Smuzhiyun		reg = <0x13420100 0xC0>, <0x13420400 0x20>;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun		#dma-cells = <2>;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_DMA>;
429*4882a593Smuzhiyun		interrupt-parent = <&intc>;
430*4882a593Smuzhiyun		interrupts = <23>;
431*4882a593Smuzhiyun	};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun	uhc: uhc@13430000 {
434*4882a593Smuzhiyun		compatible = "generic-ohci";
435*4882a593Smuzhiyun		reg = <0x13430000 0x1000>;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
438*4882a593Smuzhiyun		assigned-clocks = <&cgu JZ4770_CLK_UHC>;
439*4882a593Smuzhiyun		assigned-clock-rates = <48000000>;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun		interrupt-parent = <&intc>;
442*4882a593Smuzhiyun		interrupts = <20>;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun		status = "disabled";
445*4882a593Smuzhiyun	};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun	usb_otg: usb@13440000 {
448*4882a593Smuzhiyun		compatible = "ingenic,jz4770-musb";
449*4882a593Smuzhiyun		reg = <0x13440000 0x10000>;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun		clocks = <&cgu JZ4770_CLK_OTG>;
452*4882a593Smuzhiyun		clock-names = "udc";
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun		interrupt-parent = <&intc>;
455*4882a593Smuzhiyun		interrupts = <21>;
456*4882a593Smuzhiyun		interrupt-names = "mc";
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun		phys = <&otg_phy>;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun		usb-role-switch;
461*4882a593Smuzhiyun	};
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun	rom: memory@1fc00000 {
464*4882a593Smuzhiyun		compatible = "mtd-rom";
465*4882a593Smuzhiyun		probe-type = "map_rom";
466*4882a593Smuzhiyun		reg = <0x1fc00000 0x2000>;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun		bank-width = <4>;
469*4882a593Smuzhiyun		device-width = <1>;
470*4882a593Smuzhiyun	};
471*4882a593Smuzhiyun};
472