1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun model = "sandbox"; 5*4882a593Smuzhiyun compatible = "sandbox"; 6*4882a593Smuzhiyun #address-cells = <1>; 7*4882a593Smuzhiyun #size-cells = <1>; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun aliases { 10*4882a593Smuzhiyun console = &uart0; 11*4882a593Smuzhiyun eth0 = "/eth@10002000"; 12*4882a593Smuzhiyun eth3 = ð_3; 13*4882a593Smuzhiyun eth5 = ð_5; 14*4882a593Smuzhiyun i2c0 = "/i2c@0"; 15*4882a593Smuzhiyun mmc0 = "/mmc0"; 16*4882a593Smuzhiyun mmc1 = "/mmc1"; 17*4882a593Smuzhiyun pci0 = &pci; 18*4882a593Smuzhiyun remoteproc1 = &rproc_1; 19*4882a593Smuzhiyun remoteproc2 = &rproc_2; 20*4882a593Smuzhiyun rtc0 = &rtc_0; 21*4882a593Smuzhiyun rtc1 = &rtc_1; 22*4882a593Smuzhiyun spi0 = "/spi@0"; 23*4882a593Smuzhiyun testfdt6 = "/e-test"; 24*4882a593Smuzhiyun testbus3 = "/some-bus"; 25*4882a593Smuzhiyun testfdt0 = "/some-bus/c-test@0"; 26*4882a593Smuzhiyun testfdt1 = "/some-bus/c-test@1"; 27*4882a593Smuzhiyun testfdt3 = "/b-test"; 28*4882a593Smuzhiyun testfdt5 = "/some-bus/c-test@5"; 29*4882a593Smuzhiyun testfdt8 = "/a-test"; 30*4882a593Smuzhiyun usb0 = &usb_0; 31*4882a593Smuzhiyun usb1 = &usb_1; 32*4882a593Smuzhiyun usb2 = &usb_2; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun a-test { 36*4882a593Smuzhiyun reg = <0 1>; 37*4882a593Smuzhiyun compatible = "denx,u-boot-fdt-test"; 38*4882a593Smuzhiyun ping-expect = <0>; 39*4882a593Smuzhiyun ping-add = <0>; 40*4882a593Smuzhiyun u-boot,dm-pre-reloc; 41*4882a593Smuzhiyun test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>, 42*4882a593Smuzhiyun <0>, <&gpio_a 12>; 43*4882a593Smuzhiyun test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>, 44*4882a593Smuzhiyun <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>, 45*4882a593Smuzhiyun <&gpio_b 9 0xc 3 2 1>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun junk { 49*4882a593Smuzhiyun reg = <1 1>; 50*4882a593Smuzhiyun compatible = "not,compatible"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun no-compatible { 54*4882a593Smuzhiyun reg = <2 1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun b-test { 58*4882a593Smuzhiyun reg = <3 1>; 59*4882a593Smuzhiyun compatible = "denx,u-boot-fdt-test"; 60*4882a593Smuzhiyun ping-expect = <3>; 61*4882a593Smuzhiyun ping-add = <3>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun phy_provider0: gen_phy@0 { 65*4882a593Smuzhiyun compatible = "sandbox,phy"; 66*4882a593Smuzhiyun #phy-cells = <1>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun phy_provider1: gen_phy@1 { 70*4882a593Smuzhiyun compatible = "sandbox,phy"; 71*4882a593Smuzhiyun #phy-cells = <0>; 72*4882a593Smuzhiyun broken; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun gen_phy_user: gen_phy_user { 76*4882a593Smuzhiyun compatible = "simple-bus"; 77*4882a593Smuzhiyun phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>; 78*4882a593Smuzhiyun phy-names = "phy1", "phy2", "phy3"; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun some-bus { 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun #size-cells = <0>; 84*4882a593Smuzhiyun compatible = "denx,u-boot-test-bus"; 85*4882a593Smuzhiyun reg = <3 1>; 86*4882a593Smuzhiyun ping-expect = <4>; 87*4882a593Smuzhiyun ping-add = <4>; 88*4882a593Smuzhiyun c-test@5 { 89*4882a593Smuzhiyun compatible = "denx,u-boot-fdt-test"; 90*4882a593Smuzhiyun reg = <5>; 91*4882a593Smuzhiyun ping-expect = <5>; 92*4882a593Smuzhiyun ping-add = <5>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun c-test@0 { 95*4882a593Smuzhiyun compatible = "denx,u-boot-fdt-test"; 96*4882a593Smuzhiyun reg = <0>; 97*4882a593Smuzhiyun ping-expect = <6>; 98*4882a593Smuzhiyun ping-add = <6>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun c-test@1 { 101*4882a593Smuzhiyun compatible = "denx,u-boot-fdt-test"; 102*4882a593Smuzhiyun reg = <1>; 103*4882a593Smuzhiyun ping-expect = <7>; 104*4882a593Smuzhiyun ping-add = <7>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun d-test { 109*4882a593Smuzhiyun reg = <3 1>; 110*4882a593Smuzhiyun ping-expect = <6>; 111*4882a593Smuzhiyun ping-add = <6>; 112*4882a593Smuzhiyun compatible = "google,another-fdt-test"; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun e-test { 116*4882a593Smuzhiyun reg = <3 1>; 117*4882a593Smuzhiyun ping-expect = <6>; 118*4882a593Smuzhiyun ping-add = <6>; 119*4882a593Smuzhiyun compatible = "google,another-fdt-test"; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun f-test { 123*4882a593Smuzhiyun compatible = "denx,u-boot-fdt-test"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun g-test { 127*4882a593Smuzhiyun compatible = "denx,u-boot-fdt-test"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun clocks { 131*4882a593Smuzhiyun clk_fixed: clk-fixed { 132*4882a593Smuzhiyun compatible = "fixed-clock"; 133*4882a593Smuzhiyun #clock-cells = <0>; 134*4882a593Smuzhiyun clock-frequency = <1234>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun clk_sandbox: clk-sbox { 139*4882a593Smuzhiyun compatible = "sandbox,clk"; 140*4882a593Smuzhiyun #clock-cells = <1>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun clk-test { 144*4882a593Smuzhiyun compatible = "sandbox,clk-test"; 145*4882a593Smuzhiyun clocks = <&clk_fixed>, 146*4882a593Smuzhiyun <&clk_sandbox 1>, 147*4882a593Smuzhiyun <&clk_sandbox 0>; 148*4882a593Smuzhiyun clock-names = "fixed", "i2c", "spi"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun eth@10002000 { 152*4882a593Smuzhiyun compatible = "sandbox,eth"; 153*4882a593Smuzhiyun reg = <0x10002000 0x1000>; 154*4882a593Smuzhiyun fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun eth_5: eth@10003000 { 158*4882a593Smuzhiyun compatible = "sandbox,eth"; 159*4882a593Smuzhiyun reg = <0x10003000 0x1000>; 160*4882a593Smuzhiyun fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun eth_3: sbe5 { 164*4882a593Smuzhiyun compatible = "sandbox,eth"; 165*4882a593Smuzhiyun reg = <0x10005000 0x1000>; 166*4882a593Smuzhiyun fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun eth@10004000 { 170*4882a593Smuzhiyun compatible = "sandbox,eth"; 171*4882a593Smuzhiyun reg = <0x10004000 0x1000>; 172*4882a593Smuzhiyun fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun firmware { 176*4882a593Smuzhiyun sandbox_firmware: sandbox-firmware { 177*4882a593Smuzhiyun compatible = "sandbox,firmware"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun sandbox-scmi-agent@0 { 181*4882a593Smuzhiyun compatible = "sandbox,scmi-agent"; 182*4882a593Smuzhiyun #address-cells = <1>; 183*4882a593Smuzhiyun #size-cells = <0>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun sandbox-scmi-agent@1 { 187*4882a593Smuzhiyun compatible = "sandbox,scmi-agent"; 188*4882a593Smuzhiyun #address-cells = <1>; 189*4882a593Smuzhiyun #size-cells = <0>; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun protocol@10 { 192*4882a593Smuzhiyun reg = <0x10>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun gpio_a: base-gpios { 198*4882a593Smuzhiyun compatible = "sandbox,gpio"; 199*4882a593Smuzhiyun gpio-controller; 200*4882a593Smuzhiyun #gpio-cells = <1>; 201*4882a593Smuzhiyun gpio-bank-name = "a"; 202*4882a593Smuzhiyun num-gpios = <20>; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun gpio_b: extra-gpios { 206*4882a593Smuzhiyun compatible = "sandbox,gpio"; 207*4882a593Smuzhiyun gpio-controller; 208*4882a593Smuzhiyun #gpio-cells = <5>; 209*4882a593Smuzhiyun gpio-bank-name = "b"; 210*4882a593Smuzhiyun num-gpios = <10>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun i2c@0 { 214*4882a593Smuzhiyun #address-cells = <1>; 215*4882a593Smuzhiyun #size-cells = <0>; 216*4882a593Smuzhiyun reg = <0 1>; 217*4882a593Smuzhiyun compatible = "sandbox,i2c"; 218*4882a593Smuzhiyun clock-frequency = <100000>; 219*4882a593Smuzhiyun eeprom@2c { 220*4882a593Smuzhiyun reg = <0x2c>; 221*4882a593Smuzhiyun compatible = "i2c-eeprom"; 222*4882a593Smuzhiyun emul { 223*4882a593Smuzhiyun compatible = "sandbox,i2c-eeprom"; 224*4882a593Smuzhiyun sandbox,filename = "i2c.bin"; 225*4882a593Smuzhiyun sandbox,size = <256>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun rtc_0: rtc@43 { 230*4882a593Smuzhiyun reg = <0x43>; 231*4882a593Smuzhiyun compatible = "sandbox-rtc"; 232*4882a593Smuzhiyun emul { 233*4882a593Smuzhiyun compatible = "sandbox,i2c-rtc"; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun rtc_1: rtc@61 { 238*4882a593Smuzhiyun reg = <0x61>; 239*4882a593Smuzhiyun compatible = "sandbox-rtc"; 240*4882a593Smuzhiyun emul { 241*4882a593Smuzhiyun compatible = "sandbox,i2c-rtc"; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun sandbox_pmic: sandbox_pmic { 246*4882a593Smuzhiyun reg = <0x40>; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun adc@0 { 251*4882a593Smuzhiyun compatible = "sandbox,adc"; 252*4882a593Smuzhiyun vdd-supply = <&buck2>; 253*4882a593Smuzhiyun vss-microvolts = <0>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun lcd { 257*4882a593Smuzhiyun u-boot,dm-pre-reloc; 258*4882a593Smuzhiyun compatible = "sandbox,lcd-sdl"; 259*4882a593Smuzhiyun xres = <1366>; 260*4882a593Smuzhiyun yres = <768>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun leds { 264*4882a593Smuzhiyun compatible = "gpio-leds"; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun iracibble { 267*4882a593Smuzhiyun gpios = <&gpio_a 1 0>; 268*4882a593Smuzhiyun label = "sandbox:red"; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun martinet { 272*4882a593Smuzhiyun gpios = <&gpio_a 2 0>; 273*4882a593Smuzhiyun label = "sandbox:green"; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun mbox: mbox { 278*4882a593Smuzhiyun compatible = "sandbox,mbox"; 279*4882a593Smuzhiyun #mbox-cells = <1>; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun mbox-test { 283*4882a593Smuzhiyun compatible = "sandbox,mbox-test"; 284*4882a593Smuzhiyun mboxes = <&mbox 100>, <&mbox 1>; 285*4882a593Smuzhiyun mbox-names = "other", "test"; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun mmc2 { 289*4882a593Smuzhiyun compatible = "sandbox,mmc"; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun mmc1 { 293*4882a593Smuzhiyun compatible = "sandbox,mmc"; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun mmc0 { 297*4882a593Smuzhiyun compatible = "sandbox,mmc"; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun nop-test_0 { 301*4882a593Smuzhiyun compatible = "sandbox,nop_sandbox1"; 302*4882a593Smuzhiyun nop-test_1 { 303*4882a593Smuzhiyun compatible = "sandbox,nop_sandbox2"; 304*4882a593Smuzhiyun bind = "True"; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun nop-test_2 { 307*4882a593Smuzhiyun compatible = "sandbox,nop_sandbox2"; 308*4882a593Smuzhiyun bind = "False"; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun pci: pci-controller { 313*4882a593Smuzhiyun compatible = "sandbox,pci"; 314*4882a593Smuzhiyun device_type = "pci"; 315*4882a593Smuzhiyun #address-cells = <3>; 316*4882a593Smuzhiyun #size-cells = <2>; 317*4882a593Smuzhiyun ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000 318*4882a593Smuzhiyun 0x01000000 0 0x20000000 0x20000000 0 0x2000>; 319*4882a593Smuzhiyun pci@1f,0 { 320*4882a593Smuzhiyun compatible = "pci-generic"; 321*4882a593Smuzhiyun reg = <0xf800 0 0 0 0>; 322*4882a593Smuzhiyun emul@1f,0 { 323*4882a593Smuzhiyun compatible = "sandbox,swap-case"; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun probing { 329*4882a593Smuzhiyun compatible = "simple-bus"; 330*4882a593Smuzhiyun test1 { 331*4882a593Smuzhiyun compatible = "denx,u-boot-probe-test"; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun test2 { 335*4882a593Smuzhiyun compatible = "denx,u-boot-probe-test"; 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun test3 { 339*4882a593Smuzhiyun compatible = "denx,u-boot-probe-test"; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun test4 { 343*4882a593Smuzhiyun compatible = "denx,u-boot-probe-test"; 344*4882a593Smuzhiyun first-syscon = <&syscon0>; 345*4882a593Smuzhiyun second-sys-ctrl = <&another_system_controller>; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun pwrdom: power-domain { 350*4882a593Smuzhiyun compatible = "sandbox,power-domain"; 351*4882a593Smuzhiyun #power-domain-cells = <1>; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun power-domain-test { 355*4882a593Smuzhiyun compatible = "sandbox,power-domain-test"; 356*4882a593Smuzhiyun power-domains = <&pwrdom 2>; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun pwm { 360*4882a593Smuzhiyun compatible = "sandbox,pwm"; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun pwm2 { 364*4882a593Smuzhiyun compatible = "sandbox,pwm"; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun ram { 368*4882a593Smuzhiyun compatible = "sandbox,ram"; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun reset@0 { 372*4882a593Smuzhiyun compatible = "sandbox,warm-reset"; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun reset@1 { 376*4882a593Smuzhiyun compatible = "sandbox,reset"; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun resetc: reset-ctl { 380*4882a593Smuzhiyun compatible = "sandbox,reset-ctl"; 381*4882a593Smuzhiyun #reset-cells = <1>; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun reset-ctl-test { 385*4882a593Smuzhiyun compatible = "sandbox,reset-ctl-test"; 386*4882a593Smuzhiyun resets = <&resetc 100>, <&resetc 2>; 387*4882a593Smuzhiyun reset-names = "other", "test"; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun rproc_1: rproc@1 { 391*4882a593Smuzhiyun compatible = "sandbox,test-processor"; 392*4882a593Smuzhiyun remoteproc-name = "remoteproc-test-dev1"; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun rproc_2: rproc@2 { 396*4882a593Smuzhiyun compatible = "sandbox,test-processor"; 397*4882a593Smuzhiyun internal-memory-mapped; 398*4882a593Smuzhiyun remoteproc-name = "remoteproc-test-dev2"; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun spi@0 { 402*4882a593Smuzhiyun #address-cells = <1>; 403*4882a593Smuzhiyun #size-cells = <0>; 404*4882a593Smuzhiyun reg = <0 1>; 405*4882a593Smuzhiyun compatible = "sandbox,spi"; 406*4882a593Smuzhiyun cs-gpios = <0>, <&gpio_a 0>; 407*4882a593Smuzhiyun spi.bin@0 { 408*4882a593Smuzhiyun reg = <0>; 409*4882a593Smuzhiyun compatible = "spansion,m25p16", "spi-flash"; 410*4882a593Smuzhiyun spi-max-frequency = <40000000>; 411*4882a593Smuzhiyun sandbox,filename = "spi.bin"; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun syscon0: syscon@0 { 416*4882a593Smuzhiyun compatible = "sandbox,syscon0"; 417*4882a593Smuzhiyun reg = <0x10 4>; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun another_system_controller: syscon@1 { 421*4882a593Smuzhiyun compatible = "sandbox,syscon1"; 422*4882a593Smuzhiyun reg = <0x20 5 423*4882a593Smuzhiyun 0x28 6 424*4882a593Smuzhiyun 0x30 7 425*4882a593Smuzhiyun 0x38 8>; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun timer { 429*4882a593Smuzhiyun compatible = "sandbox,timer"; 430*4882a593Smuzhiyun clock-frequency = <1000000>; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun uart0: serial { 434*4882a593Smuzhiyun compatible = "sandbox,serial"; 435*4882a593Smuzhiyun u-boot,dm-pre-reloc; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun usb_0: usb@0 { 439*4882a593Smuzhiyun compatible = "sandbox,usb"; 440*4882a593Smuzhiyun status = "disabled"; 441*4882a593Smuzhiyun hub { 442*4882a593Smuzhiyun compatible = "sandbox,usb-hub"; 443*4882a593Smuzhiyun #address-cells = <1>; 444*4882a593Smuzhiyun #size-cells = <0>; 445*4882a593Smuzhiyun flash-stick { 446*4882a593Smuzhiyun reg = <0>; 447*4882a593Smuzhiyun compatible = "sandbox,usb-flash"; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun usb_1: usb@1 { 453*4882a593Smuzhiyun compatible = "sandbox,usb"; 454*4882a593Smuzhiyun hub { 455*4882a593Smuzhiyun compatible = "usb-hub"; 456*4882a593Smuzhiyun usb,device-class = <9>; 457*4882a593Smuzhiyun hub-emul { 458*4882a593Smuzhiyun compatible = "sandbox,usb-hub"; 459*4882a593Smuzhiyun #address-cells = <1>; 460*4882a593Smuzhiyun #size-cells = <0>; 461*4882a593Smuzhiyun flash-stick@0 { 462*4882a593Smuzhiyun reg = <0>; 463*4882a593Smuzhiyun compatible = "sandbox,usb-flash"; 464*4882a593Smuzhiyun sandbox,filepath = "testflash.bin"; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun flash-stick@1 { 468*4882a593Smuzhiyun reg = <1>; 469*4882a593Smuzhiyun compatible = "sandbox,usb-flash"; 470*4882a593Smuzhiyun sandbox,filepath = "testflash1.bin"; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun flash-stick@2 { 474*4882a593Smuzhiyun reg = <2>; 475*4882a593Smuzhiyun compatible = "sandbox,usb-flash"; 476*4882a593Smuzhiyun sandbox,filepath = "testflash2.bin"; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun keyb@3 { 480*4882a593Smuzhiyun reg = <3>; 481*4882a593Smuzhiyun compatible = "sandbox,usb-keyb"; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun }; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun usb_2: usb@2 { 489*4882a593Smuzhiyun compatible = "sandbox,usb"; 490*4882a593Smuzhiyun status = "disabled"; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun spmi: spmi@0 { 494*4882a593Smuzhiyun compatible = "sandbox,spmi"; 495*4882a593Smuzhiyun #address-cells = <0x1>; 496*4882a593Smuzhiyun #size-cells = <0x1>; 497*4882a593Smuzhiyun pm8916@0 { 498*4882a593Smuzhiyun compatible = "qcom,spmi-pmic"; 499*4882a593Smuzhiyun reg = <0x0 0x1>; 500*4882a593Smuzhiyun #address-cells = <0x1>; 501*4882a593Smuzhiyun #size-cells = <0x1>; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun spmi_gpios: gpios@c000 { 504*4882a593Smuzhiyun compatible = "qcom,pm8916-gpio"; 505*4882a593Smuzhiyun reg = <0xc000 0x400>; 506*4882a593Smuzhiyun gpio-controller; 507*4882a593Smuzhiyun gpio-count = <4>; 508*4882a593Smuzhiyun #gpio-cells = <2>; 509*4882a593Smuzhiyun gpio-bank-name="spmi"; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun wdt0: wdt@0 { 515*4882a593Smuzhiyun compatible = "sandbox,wdt"; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun}; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun#include "sandbox_pmic.dtsi" 520