Home
last modified time | relevance | path

Searched +full:0 +full:x0400 (Results 1 – 25 of 1074) sorted by relevance

12345678910>>...43

/OK3568_Linux_fs/kernel/include/linux/mfd/wm8350/
H A Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
H A Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
H A Dpmic.h19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
H A Dgf100.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_ibus_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_ibus_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_ibus_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_ibus_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_ibus_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_ibus_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_ibus_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_ibus_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); in gf100_ibus_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x121c58); in gf100_ibus_intr()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A Dcs8900.h57 #define ISQ_RxEvent 0x04
58 #define ISQ_TxEvent 0x08
59 #define ISQ_BufEvent 0x0C
60 #define ISQ_RxMissEvent 0x10
61 #define ISQ_TxColEvent 0x12
62 #define ISQ_EventMask 0x3F
67 #define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
68 #define PP_ChipRev 0x0002 /* Chip revision, model codes */
70 #define PP_IntReg 0x0022 /* Interrupt configuration */
71 #define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/cirrus/
H A Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/asm/
H A Dsmc37c93x.h14 #define FDC_PRIMARY_BASE 0x3f0
15 #define IDE1_PRIMARY_BASE 0x1f0
16 #define IDE1_SECONDARY_BASE 0x170
17 #define PARPORT_PRIMARY_BASE 0x378
18 #define COM1_PRIMARY_BASE 0x2f8
19 #define COM2_PRIMARY_BASE 0x3f8
20 #define RTC_PRIMARY_BASE 0x070
21 #define KBC_PRIMARY_BASE 0x060
22 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
25 #define LDN_FDC 0
[all …]
/OK3568_Linux_fs/external/camera_engine_rkaiq/rkisp_demo/demo/sample/
H A Dsample_abayertnr_module.cpp23 printf("\t 0) ABAYERTNR: get abayertnr attri on sync mode.\n"); in sample_abayertnr_usage()
127 for(int i = 0; i < RK_BAYERNR_V2_MAX_ISO_NUM; i++) { in sample_abayertnr_setAuto_v2()
130 bayertnrV2_attr.stAuto.st3DParams.lumapoint[0] = 512; in sample_abayertnr_setAuto_v2()
147 bayertnrV2_attr.stAuto.st3DParams.sigma[i][0] = 90; in sample_abayertnr_setAuto_v2()
164 bayertnrV2_attr.stAuto.st3DParams.lumapoint2[0] = 512; in sample_abayertnr_setAuto_v2()
182 bayertnrV2_attr.stAuto.st3DParams.lo_sigma[i][0] = 90; in sample_abayertnr_setAuto_v2()
199 bayertnrV2_attr.stAuto.st3DParams.hi_sigma[i][0] = 90; in sample_abayertnr_setAuto_v2()
224 bayertnrV2_attr.stAuto.st3DParams.global_pk_en[i] = 0; in sample_abayertnr_setAuto_v2()
258 for(int i = 0; i < RK_BAYERNR_V23_MAX_ISO_NUM; i++) { in sample_abayertnr_setAuto_v23()
261 bayertnr_attr.stAuto.st3DParams.bayertnrParamISO[i].lumapoint[0] = 512; in sample_abayertnr_setAuto_v23()
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dwm8400-private.h16 #define WM8400_REGISTER_COUNT 0x55
28 #define WM8400_RESET_ID 0x00
29 #define WM8400_ID 0x01
30 #define WM8400_POWER_MANAGEMENT_1 0x02
31 #define WM8400_POWER_MANAGEMENT_2 0x03
32 #define WM8400_POWER_MANAGEMENT_3 0x04
33 #define WM8400_AUDIO_INTERFACE_1 0x05
34 #define WM8400_AUDIO_INTERFACE_2 0x06
35 #define WM8400_CLOCKING_1 0x07
36 #define WM8400_CLOCKING_2 0x08
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7915/
H A Ddma.c18 err = mt76_queue_alloc(dev, hwq, MT7915_TXQ_BAND0, n_desc, 0, in mt7915_init_tx_queues()
20 if (err < 0) in mt7915_init_tx_queues()
23 for (i = 0; i < MT_TXQ_MCU; i++) in mt7915_init_tx_queues()
26 return 0; in mt7915_init_tx_queues()
39 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE); in mt7915_init_mcu_queue()
40 if (err < 0) in mt7915_init_mcu_queue()
45 return 0; in mt7915_init_mcu_queue()
55 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); in mt7915_queue_rx_skb()
91 if (napi_complete_done(napi, 0)) in mt7915_poll_tx()
94 return 0; in mt7915_poll_tx()
[all …]
/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Dmii.h16 #define MII_BMCR 0x00 /* Basic mode control register */
17 #define MII_BMSR 0x01 /* Basic mode status register */
18 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
19 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
20 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
21 #define MII_LPA 0x05 /* Link partner ability reg */
22 #define MII_EXPANSION 0x06 /* Expansion register */
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
25 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/wm831x/
H A Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
H A Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
H A Dpmu.h14 * R16387 (0x4003) - Power State
16 #define WM831X_CHIP_ON 0x8000 /* CHIP_ON */
17 #define WM831X_CHIP_ON_MASK 0x8000 /* CHIP_ON */
20 #define WM831X_CHIP_SLP 0x4000 /* CHIP_SLP */
21 #define WM831X_CHIP_SLP_MASK 0x4000 /* CHIP_SLP */
24 #define WM831X_REF_LP 0x1000 /* REF_LP */
25 #define WM831X_REF_LP_MASK 0x1000 /* REF_LP */
28 #define WM831X_PWRSTATE_DLY_MASK 0x0C00 /* PWRSTATE_DLY - [11:10] */
31 #define WM831X_SWRST_DLY 0x0200 /* SWRST_DLY */
32 #define WM831X_SWRST_DLY_MASK 0x0200 /* SWRST_DLY */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/amd/
H A Dam79c961a.h9 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
15 #define NET_DEBUG 0
18 #define NET_UID 0
19 #define NET_RDP 0x10
20 #define NET_RAP 0x12
21 #define NET_RESET 0x14
22 #define NET_IDP 0x16
27 #define CSR0 0
28 #define CSR0_INIT 0x0001
29 #define CSR0_STRT 0x0002
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/ti-vpe/
H A Dcsc.c51 0x0400, 0x0000, 0x057D, 0x0400, 0x1EA7, 0x1D35,
52 0x0400, 0x06EF, 0x1FFE, 0x0D40, 0x0210, 0x0C88,
57 0x04A8, 0x1FFE, 0x0662, 0x04A8, 0x1E6F, 0x1CBF,
58 0x04A8, 0x0812, 0x1FFF, 0x0C84, 0x0220, 0x0BAC,
65 0x0400, 0x0000, 0x0629, 0x0400, 0x1F45, 0x1E2B,
66 0x0400, 0x0742, 0x0000, 0x0CEC, 0x0148, 0x0C60,
71 0x04A8, 0x0000, 0x072C, 0x04A8, 0x1F26, 0x1DDE,
72 0x04A8, 0x0873, 0x0000, 0x0C20, 0x0134, 0x0B7C,
81 0x0132, 0x0259, 0x0075, 0x1F50, 0x1EA5, 0x020B,
82 0x020B, 0x1E4A, 0x1FAB, 0x0000, 0x0200, 0x0200,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/seeq/
H A Dether3.h13 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
19 #define NET_DEBUG 0
25 #define REG_COMMAND (priv(dev)->seeq + 0x0000)
26 #define CMD_ENINTDMA 0x0001
27 #define CMD_ENINTRX 0x0002
28 #define CMD_ENINTTX 0x0004
29 #define CMD_ENINTBUFWIN 0x0008
30 #define CMD_ACKINTDMA 0x0010
31 #define CMD_ACKINTRX 0x0020
32 #define CMD_ACKINTTX 0x0040
[all …]
/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/atheros/atlx/
H A Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/linux/
H A Dmii.h16 #define MII_BMCR 0x00 /* Basic mode control register */
17 #define MII_BMSR 0x01 /* Basic mode status register */
18 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
19 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
20 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
21 #define MII_LPA 0x05 /* Link partner ability reg */
22 #define MII_EXPANSION 0x06 /* Expansion register */
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
25 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/
H A Dmii.h16 #define MII_BMCR 0x00 /* Basic mode control register */
17 #define MII_BMSR 0x01 /* Basic mode status register */
18 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
19 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
20 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
21 #define MII_LPA 0x05 /* Link partner ability reg */
22 #define MII_EXPANSION 0x06 /* Expansion register */
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
25 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
[all …]
/OK3568_Linux_fs/kernel/include/soc/fsl/
H A Dcpm.h54 u8 res6[0x22];
61 #define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
62 #define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
63 #define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
64 #define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
66 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
67 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
68 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
69 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
71 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/
H A Dm66592-udc.h16 #define M66592_SYSCFG 0x00
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
18 #define M66592_XTAL48 0x8000 /* 48MHz */
19 #define M66592_XTAL24 0x4000 /* 24MHz */
20 #define M66592_XTAL12 0x0000 /* 12MHz */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
23 #define M66592_PLLC 0x0800 /* b11: PLL control */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
[all …]

12345678910>>...43