1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/mii.h: definitions for MII-compatible transceivers 4*4882a593Smuzhiyun * Originally drivers/net/sunhme.h. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _UAPI__LINUX_MII_H__ 10*4882a593Smuzhiyun #define _UAPI__LINUX_MII_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun #include <linux/ethtool.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Generic MII registers. */ 16*4882a593Smuzhiyun #define MII_BMCR 0x00 /* Basic mode control register */ 17*4882a593Smuzhiyun #define MII_BMSR 0x01 /* Basic mode status register */ 18*4882a593Smuzhiyun #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 19*4882a593Smuzhiyun #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 20*4882a593Smuzhiyun #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 21*4882a593Smuzhiyun #define MII_LPA 0x05 /* Link partner ability reg */ 22*4882a593Smuzhiyun #define MII_EXPANSION 0x06 /* Expansion register */ 23*4882a593Smuzhiyun #define MII_CTRL1000 0x09 /* 1000BASE-T control */ 24*4882a593Smuzhiyun #define MII_STAT1000 0x0a /* 1000BASE-T status */ 25*4882a593Smuzhiyun #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 26*4882a593Smuzhiyun #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 27*4882a593Smuzhiyun #define MII_ESTATUS 0x0f /* Extended Status */ 28*4882a593Smuzhiyun #define MII_DCOUNTER 0x12 /* Disconnect counter */ 29*4882a593Smuzhiyun #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 30*4882a593Smuzhiyun #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 31*4882a593Smuzhiyun #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 32*4882a593Smuzhiyun #define MII_SREVISION 0x16 /* Silicon revision */ 33*4882a593Smuzhiyun #define MII_RESV1 0x17 /* Reserved... */ 34*4882a593Smuzhiyun #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 35*4882a593Smuzhiyun #define MII_PHYADDR 0x19 /* PHY address */ 36*4882a593Smuzhiyun #define MII_RESV2 0x1a /* Reserved... */ 37*4882a593Smuzhiyun #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 38*4882a593Smuzhiyun #define MII_NCONFIG 0x1c /* Network interface config */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Basic mode control register. */ 41*4882a593Smuzhiyun #define BMCR_RESV 0x003f /* Unused... */ 42*4882a593Smuzhiyun #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ 43*4882a593Smuzhiyun #define BMCR_CTST 0x0080 /* Collision test */ 44*4882a593Smuzhiyun #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 45*4882a593Smuzhiyun #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 46*4882a593Smuzhiyun #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ 47*4882a593Smuzhiyun #define BMCR_PDOWN 0x0800 /* Enable low power state */ 48*4882a593Smuzhiyun #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 49*4882a593Smuzhiyun #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 50*4882a593Smuzhiyun #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 51*4882a593Smuzhiyun #define BMCR_RESET 0x8000 /* Reset to default state */ 52*4882a593Smuzhiyun #define BMCR_SPEED10 0x0000 /* Select 10Mbps */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Basic mode status register. */ 55*4882a593Smuzhiyun #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 56*4882a593Smuzhiyun #define BMSR_JCD 0x0002 /* Jabber detected */ 57*4882a593Smuzhiyun #define BMSR_LSTATUS 0x0004 /* Link status */ 58*4882a593Smuzhiyun #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 59*4882a593Smuzhiyun #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 60*4882a593Smuzhiyun #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 61*4882a593Smuzhiyun #define BMSR_RESV 0x00c0 /* Unused... */ 62*4882a593Smuzhiyun #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ 63*4882a593Smuzhiyun #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ 64*4882a593Smuzhiyun #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ 65*4882a593Smuzhiyun #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 66*4882a593Smuzhiyun #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 67*4882a593Smuzhiyun #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 68*4882a593Smuzhiyun #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 69*4882a593Smuzhiyun #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Advertisement control register. */ 72*4882a593Smuzhiyun #define ADVERTISE_SLCT 0x001f /* Selector bits */ 73*4882a593Smuzhiyun #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 74*4882a593Smuzhiyun #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 75*4882a593Smuzhiyun #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ 76*4882a593Smuzhiyun #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 77*4882a593Smuzhiyun #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ 78*4882a593Smuzhiyun #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 79*4882a593Smuzhiyun #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ 80*4882a593Smuzhiyun #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 81*4882a593Smuzhiyun #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ 82*4882a593Smuzhiyun #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 83*4882a593Smuzhiyun #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 84*4882a593Smuzhiyun #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ 85*4882a593Smuzhiyun #define ADVERTISE_RESV 0x1000 /* Unused... */ 86*4882a593Smuzhiyun #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 87*4882a593Smuzhiyun #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 88*4882a593Smuzhiyun #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 91*4882a593Smuzhiyun ADVERTISE_CSMA) 92*4882a593Smuzhiyun #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 93*4882a593Smuzhiyun ADVERTISE_100HALF | ADVERTISE_100FULL) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Link partner ability register. */ 96*4882a593Smuzhiyun #define LPA_SLCT 0x001f /* Same as advertise selector */ 97*4882a593Smuzhiyun #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 98*4882a593Smuzhiyun #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ 99*4882a593Smuzhiyun #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 100*4882a593Smuzhiyun #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ 101*4882a593Smuzhiyun #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 102*4882a593Smuzhiyun #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ 103*4882a593Smuzhiyun #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 104*4882a593Smuzhiyun #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ 105*4882a593Smuzhiyun #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 106*4882a593Smuzhiyun #define LPA_PAUSE_CAP 0x0400 /* Can pause */ 107*4882a593Smuzhiyun #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ 108*4882a593Smuzhiyun #define LPA_RESV 0x1000 /* Unused... */ 109*4882a593Smuzhiyun #define LPA_RFAULT 0x2000 /* Link partner faulted */ 110*4882a593Smuzhiyun #define LPA_LPACK 0x4000 /* Link partner acked us */ 111*4882a593Smuzhiyun #define LPA_NPAGE 0x8000 /* Next page bit */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 114*4882a593Smuzhiyun #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* Expansion register for auto-negotiation. */ 117*4882a593Smuzhiyun #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ 118*4882a593Smuzhiyun #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ 119*4882a593Smuzhiyun #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ 120*4882a593Smuzhiyun #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ 121*4882a593Smuzhiyun #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ 122*4882a593Smuzhiyun #define EXPANSION_RESV 0xffe0 /* Unused... */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BaseX Full */ 125*4882a593Smuzhiyun #define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BaseX Half */ 126*4882a593Smuzhiyun #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ 127*4882a593Smuzhiyun #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* N-way test register. */ 130*4882a593Smuzhiyun #define NWAYTEST_RESV1 0x00ff /* Unused... */ 131*4882a593Smuzhiyun #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ 132*4882a593Smuzhiyun #define NWAYTEST_RESV2 0xfe00 /* Unused... */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* MAC and PHY tx_config_Reg[15:0] for SGMII in-band auto-negotiation.*/ 135*4882a593Smuzhiyun #define ADVERTISE_SGMII 0x0001 /* MAC can do SGMII */ 136*4882a593Smuzhiyun #define LPA_SGMII 0x0001 /* PHY can do SGMII */ 137*4882a593Smuzhiyun #define LPA_SGMII_SPD_MASK 0x0c00 /* SGMII speed mask */ 138*4882a593Smuzhiyun #define LPA_SGMII_FULL_DUPLEX 0x1000 /* SGMII full duplex */ 139*4882a593Smuzhiyun #define LPA_SGMII_DPX_SPD_MASK 0x1C00 /* SGMII duplex and speed bits */ 140*4882a593Smuzhiyun #define LPA_SGMII_10 0x0000 /* 10Mbps */ 141*4882a593Smuzhiyun #define LPA_SGMII_10HALF 0x0000 /* Can do 10mbps half-duplex */ 142*4882a593Smuzhiyun #define LPA_SGMII_10FULL 0x1000 /* Can do 10mbps full-duplex */ 143*4882a593Smuzhiyun #define LPA_SGMII_100 0x0400 /* 100Mbps */ 144*4882a593Smuzhiyun #define LPA_SGMII_100HALF 0x0400 /* Can do 100mbps half-duplex */ 145*4882a593Smuzhiyun #define LPA_SGMII_100FULL 0x1400 /* Can do 100mbps full-duplex */ 146*4882a593Smuzhiyun #define LPA_SGMII_1000 0x0800 /* 1000Mbps */ 147*4882a593Smuzhiyun #define LPA_SGMII_1000HALF 0x0800 /* Can do 1000mbps half-duplex */ 148*4882a593Smuzhiyun #define LPA_SGMII_1000FULL 0x1800 /* Can do 1000mbps full-duplex */ 149*4882a593Smuzhiyun #define LPA_SGMII_LINK 0x8000 /* PHY link with copper-side partner */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* 1000BASE-T Control register */ 152*4882a593Smuzhiyun #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ 153*4882a593Smuzhiyun #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ 154*4882a593Smuzhiyun #define CTL1000_PREFER_MASTER 0x0400 /* prefer to operate as master */ 155*4882a593Smuzhiyun #define CTL1000_AS_MASTER 0x0800 156*4882a593Smuzhiyun #define CTL1000_ENABLE_MASTER 0x1000 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* 1000BASE-T Status register */ 159*4882a593Smuzhiyun #define LPA_1000MSFAIL 0x8000 /* Master/Slave resolution failure */ 160*4882a593Smuzhiyun #define LPA_1000MSRES 0x4000 /* Master/Slave resolution status */ 161*4882a593Smuzhiyun #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ 162*4882a593Smuzhiyun #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ 163*4882a593Smuzhiyun #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ 164*4882a593Smuzhiyun #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* Flow control flags */ 167*4882a593Smuzhiyun #define FLOW_CTRL_TX 0x01 168*4882a593Smuzhiyun #define FLOW_CTRL_RX 0x02 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* MMD Access Control register fields */ 171*4882a593Smuzhiyun #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ 172*4882a593Smuzhiyun #define MII_MMD_CTRL_ADDR 0x0000 /* Address */ 173*4882a593Smuzhiyun #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ 174*4882a593Smuzhiyun #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ 175*4882a593Smuzhiyun #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* This structure is used in all SIOCxMIIxxx ioctl calls */ 178*4882a593Smuzhiyun struct mii_ioctl_data { 179*4882a593Smuzhiyun __u16 phy_id; 180*4882a593Smuzhiyun __u16 reg_num; 181*4882a593Smuzhiyun __u16 val_in; 182*4882a593Smuzhiyun __u16 val_out; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #endif /* _UAPI__LINUX_MII_H__ */ 186