1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Author: Rahul Sharma <rahul.sharma@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Common Clock Framework support for Exynos5260 SoC. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __CLK_EXYNOS5260_H 10*4882a593Smuzhiyun #define __CLK_EXYNOS5260_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun *Registers for CMU_AUD 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define MUX_SEL_AUD 0x0200 16*4882a593Smuzhiyun #define MUX_ENABLE_AUD 0x0300 17*4882a593Smuzhiyun #define MUX_STAT_AUD 0x0400 18*4882a593Smuzhiyun #define MUX_IGNORE_AUD 0x0500 19*4882a593Smuzhiyun #define DIV_AUD0 0x0600 20*4882a593Smuzhiyun #define DIV_AUD1 0x0604 21*4882a593Smuzhiyun #define DIV_STAT_AUD0 0x0700 22*4882a593Smuzhiyun #define DIV_STAT_AUD1 0x0704 23*4882a593Smuzhiyun #define EN_ACLK_AUD 0x0800 24*4882a593Smuzhiyun #define EN_PCLK_AUD 0x0900 25*4882a593Smuzhiyun #define EN_SCLK_AUD 0x0a00 26*4882a593Smuzhiyun #define EN_IP_AUD 0x0b00 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun *Registers for CMU_DISP 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define MUX_SEL_DISP0 0x0200 32*4882a593Smuzhiyun #define MUX_SEL_DISP1 0x0204 33*4882a593Smuzhiyun #define MUX_SEL_DISP2 0x0208 34*4882a593Smuzhiyun #define MUX_SEL_DISP3 0x020C 35*4882a593Smuzhiyun #define MUX_SEL_DISP4 0x0210 36*4882a593Smuzhiyun #define MUX_ENABLE_DISP0 0x0300 37*4882a593Smuzhiyun #define MUX_ENABLE_DISP1 0x0304 38*4882a593Smuzhiyun #define MUX_ENABLE_DISP2 0x0308 39*4882a593Smuzhiyun #define MUX_ENABLE_DISP3 0x030c 40*4882a593Smuzhiyun #define MUX_ENABLE_DISP4 0x0310 41*4882a593Smuzhiyun #define MUX_STAT_DISP0 0x0400 42*4882a593Smuzhiyun #define MUX_STAT_DISP1 0x0404 43*4882a593Smuzhiyun #define MUX_STAT_DISP2 0x0408 44*4882a593Smuzhiyun #define MUX_STAT_DISP3 0x040c 45*4882a593Smuzhiyun #define MUX_STAT_DISP4 0x0410 46*4882a593Smuzhiyun #define MUX_IGNORE_DISP0 0x0500 47*4882a593Smuzhiyun #define MUX_IGNORE_DISP1 0x0504 48*4882a593Smuzhiyun #define MUX_IGNORE_DISP2 0x0508 49*4882a593Smuzhiyun #define MUX_IGNORE_DISP3 0x050c 50*4882a593Smuzhiyun #define MUX_IGNORE_DISP4 0x0510 51*4882a593Smuzhiyun #define DIV_DISP 0x0600 52*4882a593Smuzhiyun #define DIV_STAT_DISP 0x0700 53*4882a593Smuzhiyun #define EN_ACLK_DISP 0x0800 54*4882a593Smuzhiyun #define EN_PCLK_DISP 0x0900 55*4882a593Smuzhiyun #define EN_SCLK_DISP0 0x0a00 56*4882a593Smuzhiyun #define EN_SCLK_DISP1 0x0a04 57*4882a593Smuzhiyun #define EN_IP_DISP 0x0b00 58*4882a593Smuzhiyun #define EN_IP_DISP_BUS 0x0b04 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun *Registers for CMU_EGL 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun #define EGL_PLL_LOCK 0x0000 65*4882a593Smuzhiyun #define EGL_DPLL_LOCK 0x0004 66*4882a593Smuzhiyun #define EGL_PLL_CON0 0x0100 67*4882a593Smuzhiyun #define EGL_PLL_CON1 0x0104 68*4882a593Smuzhiyun #define EGL_PLL_FREQ_DET 0x010c 69*4882a593Smuzhiyun #define EGL_DPLL_CON0 0x0110 70*4882a593Smuzhiyun #define EGL_DPLL_CON1 0x0114 71*4882a593Smuzhiyun #define EGL_DPLL_FREQ_DET 0x011c 72*4882a593Smuzhiyun #define MUX_SEL_EGL 0x0200 73*4882a593Smuzhiyun #define MUX_ENABLE_EGL 0x0300 74*4882a593Smuzhiyun #define MUX_STAT_EGL 0x0400 75*4882a593Smuzhiyun #define DIV_EGL 0x0600 76*4882a593Smuzhiyun #define DIV_EGL_PLL_FDET 0x0604 77*4882a593Smuzhiyun #define DIV_STAT_EGL 0x0700 78*4882a593Smuzhiyun #define DIV_STAT_EGL_PLL_FDET 0x0704 79*4882a593Smuzhiyun #define EN_ACLK_EGL 0x0800 80*4882a593Smuzhiyun #define EN_PCLK_EGL 0x0900 81*4882a593Smuzhiyun #define EN_SCLK_EGL 0x0a00 82*4882a593Smuzhiyun #define EN_IP_EGL 0x0b00 83*4882a593Smuzhiyun #define CLKOUT_CMU_EGL 0x0c00 84*4882a593Smuzhiyun #define CLKOUT_CMU_EGL_DIV_STAT 0x0c04 85*4882a593Smuzhiyun #define ARMCLK_STOPCTRL 0x1000 86*4882a593Smuzhiyun #define EAGLE_EMA_CTRL 0x1008 87*4882a593Smuzhiyun #define EAGLE_EMA_STATUS 0x100c 88*4882a593Smuzhiyun #define PWR_CTRL 0x1020 89*4882a593Smuzhiyun #define PWR_CTRL2 0x1024 90*4882a593Smuzhiyun #define CLKSTOP_CTRL 0x1028 91*4882a593Smuzhiyun #define INTR_SPREAD_EN 0x1080 92*4882a593Smuzhiyun #define INTR_SPREAD_USE_STANDBYWFI 0x1084 93*4882a593Smuzhiyun #define INTR_SPREAD_BLOCKING_DURATION 0x1088 94*4882a593Smuzhiyun #define CMU_EGL_SPARE0 0x2000 95*4882a593Smuzhiyun #define CMU_EGL_SPARE1 0x2004 96*4882a593Smuzhiyun #define CMU_EGL_SPARE2 0x2008 97*4882a593Smuzhiyun #define CMU_EGL_SPARE3 0x200c 98*4882a593Smuzhiyun #define CMU_EGL_SPARE4 0x2010 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun *Registers for CMU_FSYS 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define MUX_SEL_FSYS0 0x0200 105*4882a593Smuzhiyun #define MUX_SEL_FSYS1 0x0204 106*4882a593Smuzhiyun #define MUX_ENABLE_FSYS0 0x0300 107*4882a593Smuzhiyun #define MUX_ENABLE_FSYS1 0x0304 108*4882a593Smuzhiyun #define MUX_STAT_FSYS0 0x0400 109*4882a593Smuzhiyun #define MUX_STAT_FSYS1 0x0404 110*4882a593Smuzhiyun #define MUX_IGNORE_FSYS0 0x0500 111*4882a593Smuzhiyun #define MUX_IGNORE_FSYS1 0x0504 112*4882a593Smuzhiyun #define EN_ACLK_FSYS 0x0800 113*4882a593Smuzhiyun #define EN_ACLK_FSYS_SECURE_RTIC 0x0804 114*4882a593Smuzhiyun #define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808 115*4882a593Smuzhiyun #define EN_PCLK_FSYS 0x0900 116*4882a593Smuzhiyun #define EN_SCLK_FSYS 0x0a00 117*4882a593Smuzhiyun #define EN_IP_FSYS 0x0b00 118*4882a593Smuzhiyun #define EN_IP_FSYS_SECURE_RTIC 0x0b04 119*4882a593Smuzhiyun #define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* 122*4882a593Smuzhiyun *Registers for CMU_G2D 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define MUX_SEL_G2D 0x0200 126*4882a593Smuzhiyun #define MUX_ENABLE_G2D 0x0300 127*4882a593Smuzhiyun #define MUX_STAT_G2D 0x0400 128*4882a593Smuzhiyun #define DIV_G2D 0x0600 129*4882a593Smuzhiyun #define DIV_STAT_G2D 0x0700 130*4882a593Smuzhiyun #define EN_ACLK_G2D 0x0800 131*4882a593Smuzhiyun #define EN_ACLK_G2D_SECURE_SSS 0x0804 132*4882a593Smuzhiyun #define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808 133*4882a593Smuzhiyun #define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c 134*4882a593Smuzhiyun #define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810 135*4882a593Smuzhiyun #define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814 136*4882a593Smuzhiyun #define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818 137*4882a593Smuzhiyun #define EN_PCLK_G2D 0x0900 138*4882a593Smuzhiyun #define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904 139*4882a593Smuzhiyun #define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908 140*4882a593Smuzhiyun #define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c 141*4882a593Smuzhiyun #define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910 142*4882a593Smuzhiyun #define EN_IP_G2D 0x0b00 143*4882a593Smuzhiyun #define EN_IP_G2D_SECURE_SSS 0x0b04 144*4882a593Smuzhiyun #define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08 145*4882a593Smuzhiyun #define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c 146*4882a593Smuzhiyun #define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10 147*4882a593Smuzhiyun #define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14 148*4882a593Smuzhiyun #define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* 151*4882a593Smuzhiyun *Registers for CMU_G3D 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define G3D_PLL_LOCK 0x0000 155*4882a593Smuzhiyun #define G3D_PLL_CON0 0x0100 156*4882a593Smuzhiyun #define G3D_PLL_CON1 0x0104 157*4882a593Smuzhiyun #define G3D_PLL_FDET 0x010c 158*4882a593Smuzhiyun #define MUX_SEL_G3D 0x0200 159*4882a593Smuzhiyun #define MUX_EN_G3D 0x0300 160*4882a593Smuzhiyun #define MUX_STAT_G3D 0x0400 161*4882a593Smuzhiyun #define MUX_IGNORE_G3D 0x0500 162*4882a593Smuzhiyun #define DIV_G3D 0x0600 163*4882a593Smuzhiyun #define DIV_G3D_PLL_FDET 0x0604 164*4882a593Smuzhiyun #define DIV_STAT_G3D 0x0700 165*4882a593Smuzhiyun #define DIV_STAT_G3D_PLL_FDET 0x0704 166*4882a593Smuzhiyun #define EN_ACLK_G3D 0x0800 167*4882a593Smuzhiyun #define EN_PCLK_G3D 0x0900 168*4882a593Smuzhiyun #define EN_SCLK_G3D 0x0a00 169*4882a593Smuzhiyun #define EN_IP_G3D 0x0b00 170*4882a593Smuzhiyun #define CLKOUT_CMU_G3D 0x0c00 171*4882a593Smuzhiyun #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 172*4882a593Smuzhiyun #define G3DCLK_STOPCTRL 0x1000 173*4882a593Smuzhiyun #define G3D_EMA_CTRL 0x1008 174*4882a593Smuzhiyun #define G3D_EMA_STATUS 0x100c 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* 177*4882a593Smuzhiyun *Registers for CMU_GSCL 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define MUX_SEL_GSCL 0x0200 181*4882a593Smuzhiyun #define MUX_EN_GSCL 0x0300 182*4882a593Smuzhiyun #define MUX_STAT_GSCL 0x0400 183*4882a593Smuzhiyun #define MUX_IGNORE_GSCL 0x0500 184*4882a593Smuzhiyun #define DIV_GSCL 0x0600 185*4882a593Smuzhiyun #define DIV_STAT_GSCL 0x0700 186*4882a593Smuzhiyun #define EN_ACLK_GSCL 0x0800 187*4882a593Smuzhiyun #define EN_ACLK_GSCL_FIMC 0x0804 188*4882a593Smuzhiyun #define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808 189*4882a593Smuzhiyun #define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c 190*4882a593Smuzhiyun #define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810 191*4882a593Smuzhiyun #define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814 192*4882a593Smuzhiyun #define EN_PCLK_GSCL 0x0900 193*4882a593Smuzhiyun #define EN_PCLK_GSCL_FIMC 0x0904 194*4882a593Smuzhiyun #define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908 195*4882a593Smuzhiyun #define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c 196*4882a593Smuzhiyun #define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910 197*4882a593Smuzhiyun #define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914 198*4882a593Smuzhiyun #define EN_SCLK_GSCL 0x0a00 199*4882a593Smuzhiyun #define EN_SCLK_GSCL_FIMC 0x0a04 200*4882a593Smuzhiyun #define EN_IP_GSCL 0x0b00 201*4882a593Smuzhiyun #define EN_IP_GSCL_FIMC 0x0b04 202*4882a593Smuzhiyun #define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 203*4882a593Smuzhiyun #define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 204*4882a593Smuzhiyun #define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10 205*4882a593Smuzhiyun #define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* 208*4882a593Smuzhiyun *Registers for CMU_ISP 209*4882a593Smuzhiyun */ 210*4882a593Smuzhiyun #define MUX_SEL_ISP0 0x0200 211*4882a593Smuzhiyun #define MUX_SEL_ISP1 0x0204 212*4882a593Smuzhiyun #define MUX_ENABLE_ISP0 0x0300 213*4882a593Smuzhiyun #define MUX_ENABLE_ISP1 0x0304 214*4882a593Smuzhiyun #define MUX_STAT_ISP0 0x0400 215*4882a593Smuzhiyun #define MUX_STAT_ISP1 0x0404 216*4882a593Smuzhiyun #define MUX_IGNORE_ISP0 0x0500 217*4882a593Smuzhiyun #define MUX_IGNORE_ISP1 0x0504 218*4882a593Smuzhiyun #define DIV_ISP 0x0600 219*4882a593Smuzhiyun #define DIV_STAT_ISP 0x0700 220*4882a593Smuzhiyun #define EN_ACLK_ISP0 0x0800 221*4882a593Smuzhiyun #define EN_ACLK_ISP1 0x0804 222*4882a593Smuzhiyun #define EN_PCLK_ISP0 0x0900 223*4882a593Smuzhiyun #define EN_PCLK_ISP1 0x0904 224*4882a593Smuzhiyun #define EN_SCLK_ISP 0x0a00 225*4882a593Smuzhiyun #define EN_IP_ISP0 0x0b00 226*4882a593Smuzhiyun #define EN_IP_ISP1 0x0b04 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* 229*4882a593Smuzhiyun *Registers for CMU_KFC 230*4882a593Smuzhiyun */ 231*4882a593Smuzhiyun #define KFC_PLL_LOCK 0x0000 232*4882a593Smuzhiyun #define KFC_PLL_CON0 0x0100 233*4882a593Smuzhiyun #define KFC_PLL_CON1 0x0104 234*4882a593Smuzhiyun #define KFC_PLL_FDET 0x010c 235*4882a593Smuzhiyun #define MUX_SEL_KFC0 0x0200 236*4882a593Smuzhiyun #define MUX_SEL_KFC2 0x0208 237*4882a593Smuzhiyun #define MUX_ENABLE_KFC0 0x0300 238*4882a593Smuzhiyun #define MUX_ENABLE_KFC2 0x0308 239*4882a593Smuzhiyun #define MUX_STAT_KFC0 0x0400 240*4882a593Smuzhiyun #define MUX_STAT_KFC2 0x0408 241*4882a593Smuzhiyun #define DIV_KFC 0x0600 242*4882a593Smuzhiyun #define DIV_KFC_PLL_FDET 0x0604 243*4882a593Smuzhiyun #define DIV_STAT_KFC 0x0700 244*4882a593Smuzhiyun #define DIV_STAT_KFC_PLL_FDET 0x0704 245*4882a593Smuzhiyun #define EN_ACLK_KFC 0x0800 246*4882a593Smuzhiyun #define EN_PCLK_KFC 0x0900 247*4882a593Smuzhiyun #define EN_SCLK_KFC 0x0a00 248*4882a593Smuzhiyun #define EN_IP_KFC 0x0b00 249*4882a593Smuzhiyun #define CLKOUT_CMU_KFC 0x0c00 250*4882a593Smuzhiyun #define CLKOUT_CMU_KFC_DIV_STAT 0x0c04 251*4882a593Smuzhiyun #define ARMCLK_STOPCTRL_KFC 0x1000 252*4882a593Smuzhiyun #define ARM_EMA_CTRL 0x1008 253*4882a593Smuzhiyun #define ARM_EMA_STATUS 0x100c 254*4882a593Smuzhiyun #define PWR_CTRL_KFC 0x1020 255*4882a593Smuzhiyun #define PWR_CTRL2_KFC 0x1024 256*4882a593Smuzhiyun #define CLKSTOP_CTRL_KFC 0x1028 257*4882a593Smuzhiyun #define INTR_SPREAD_ENABLE_KFC 0x1080 258*4882a593Smuzhiyun #define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084 259*4882a593Smuzhiyun #define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088 260*4882a593Smuzhiyun #define CMU_KFC_SPARE0 0x2000 261*4882a593Smuzhiyun #define CMU_KFC_SPARE1 0x2004 262*4882a593Smuzhiyun #define CMU_KFC_SPARE2 0x2008 263*4882a593Smuzhiyun #define CMU_KFC_SPARE3 0x200c 264*4882a593Smuzhiyun #define CMU_KFC_SPARE4 0x2010 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* 267*4882a593Smuzhiyun *Registers for CMU_MFC 268*4882a593Smuzhiyun */ 269*4882a593Smuzhiyun #define MUX_SEL_MFC 0x0200 270*4882a593Smuzhiyun #define MUX_ENABLE_MFC 0x0300 271*4882a593Smuzhiyun #define MUX_STAT_MFC 0x0400 272*4882a593Smuzhiyun #define DIV_MFC 0x0600 273*4882a593Smuzhiyun #define DIV_STAT_MFC 0x0700 274*4882a593Smuzhiyun #define EN_ACLK_MFC 0x0800 275*4882a593Smuzhiyun #define EN_ACLK_SECURE_SMMU2_MFC 0x0804 276*4882a593Smuzhiyun #define EN_PCLK_MFC 0x0900 277*4882a593Smuzhiyun #define EN_PCLK_SECURE_SMMU2_MFC 0x0904 278*4882a593Smuzhiyun #define EN_IP_MFC 0x0b00 279*4882a593Smuzhiyun #define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* 282*4882a593Smuzhiyun *Registers for CMU_MIF 283*4882a593Smuzhiyun */ 284*4882a593Smuzhiyun #define MEM_PLL_LOCK 0x0000 285*4882a593Smuzhiyun #define BUS_PLL_LOCK 0x0004 286*4882a593Smuzhiyun #define MEDIA_PLL_LOCK 0x0008 287*4882a593Smuzhiyun #define MEM_PLL_CON0 0x0100 288*4882a593Smuzhiyun #define MEM_PLL_CON1 0x0104 289*4882a593Smuzhiyun #define MEM_PLL_FDET 0x010c 290*4882a593Smuzhiyun #define BUS_PLL_CON0 0x0110 291*4882a593Smuzhiyun #define BUS_PLL_CON1 0x0114 292*4882a593Smuzhiyun #define BUS_PLL_FDET 0x011c 293*4882a593Smuzhiyun #define MEDIA_PLL_CON0 0x0120 294*4882a593Smuzhiyun #define MEDIA_PLL_CON1 0x0124 295*4882a593Smuzhiyun #define MEDIA_PLL_FDET 0x012c 296*4882a593Smuzhiyun #define MUX_SEL_MIF 0x0200 297*4882a593Smuzhiyun #define MUX_ENABLE_MIF 0x0300 298*4882a593Smuzhiyun #define MUX_STAT_MIF 0x0400 299*4882a593Smuzhiyun #define MUX_IGNORE_MIF 0x0500 300*4882a593Smuzhiyun #define DIV_MIF 0x0600 301*4882a593Smuzhiyun #define DIV_MIF_PLL_FDET 0x0604 302*4882a593Smuzhiyun #define DIV_STAT_MIF 0x0700 303*4882a593Smuzhiyun #define DIV_STAT_MIF_PLL_FDET 0x0704 304*4882a593Smuzhiyun #define EN_ACLK_MIF 0x0800 305*4882a593Smuzhiyun #define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804 306*4882a593Smuzhiyun #define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808 307*4882a593Smuzhiyun #define EN_ACLK_MIF_SECURE_INTMEM 0x080c 308*4882a593Smuzhiyun #define EN_PCLK_MIF 0x0900 309*4882a593Smuzhiyun #define EN_PCLK_MIF_SECURE_MONOCNT 0x0904 310*4882a593Smuzhiyun #define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908 311*4882a593Smuzhiyun #define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c 312*4882a593Smuzhiyun #define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910 313*4882a593Smuzhiyun #define EN_SCLK_MIF 0x0a00 314*4882a593Smuzhiyun #define EN_IP_MIF 0x0b00 315*4882a593Smuzhiyun #define EN_IP_MIF_SECURE_MONOCNT 0x0b04 316*4882a593Smuzhiyun #define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08 317*4882a593Smuzhiyun #define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c 318*4882a593Smuzhiyun #define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10 319*4882a593Smuzhiyun #define EN_IP_MIF_SECURE_INTEMEM 0x0b14 320*4882a593Smuzhiyun #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 321*4882a593Smuzhiyun #define DREX_FREQ_CTRL 0x1000 322*4882a593Smuzhiyun #define PAUSE 0x1004 323*4882a593Smuzhiyun #define DDRPHY_LOCK_CTRL 0x1008 324*4882a593Smuzhiyun #define CLKOUT_CMU_MIF 0xcb00 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* 327*4882a593Smuzhiyun *Registers for CMU_PERI 328*4882a593Smuzhiyun */ 329*4882a593Smuzhiyun #define MUX_SEL_PERI 0x0200 330*4882a593Smuzhiyun #define MUX_SEL_PERI1 0x0204 331*4882a593Smuzhiyun #define MUX_ENABLE_PERI 0x0300 332*4882a593Smuzhiyun #define MUX_ENABLE_PERI1 0x0304 333*4882a593Smuzhiyun #define MUX_STAT_PERI 0x0400 334*4882a593Smuzhiyun #define MUX_STAT_PERI1 0x0404 335*4882a593Smuzhiyun #define MUX_IGNORE_PERI 0x0500 336*4882a593Smuzhiyun #define MUX_IGNORE_PERI1 0x0504 337*4882a593Smuzhiyun #define DIV_PERI 0x0600 338*4882a593Smuzhiyun #define DIV_STAT_PERI 0x0700 339*4882a593Smuzhiyun #define EN_PCLK_PERI0 0x0800 340*4882a593Smuzhiyun #define EN_PCLK_PERI1 0x0804 341*4882a593Smuzhiyun #define EN_PCLK_PERI2 0x0808 342*4882a593Smuzhiyun #define EN_PCLK_PERI3 0x080c 343*4882a593Smuzhiyun #define EN_PCLK_PERI_SECURE_CHIPID 0x0810 344*4882a593Smuzhiyun #define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814 345*4882a593Smuzhiyun #define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818 346*4882a593Smuzhiyun #define EN_PCLK_PERI_SECURE_SECKEY 0x081c 347*4882a593Smuzhiyun #define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820 348*4882a593Smuzhiyun #define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824 349*4882a593Smuzhiyun #define EN_PCLK_PERI_SECURE_TZPC 0x0828 350*4882a593Smuzhiyun #define EN_SCLK_PERI 0x0a00 351*4882a593Smuzhiyun #define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04 352*4882a593Smuzhiyun #define EN_IP_PERI0 0x0b00 353*4882a593Smuzhiyun #define EN_IP_PERI1 0x0b04 354*4882a593Smuzhiyun #define EN_IP_PERI2 0x0b08 355*4882a593Smuzhiyun #define EN_IP_PERI_SECURE_CHIPID 0x0b0c 356*4882a593Smuzhiyun #define EN_IP_PERI_SECURE_PROVKEY0 0x0b10 357*4882a593Smuzhiyun #define EN_IP_PERI_SECURE_PROVKEY1 0x0b14 358*4882a593Smuzhiyun #define EN_IP_PERI_SECURE_SECKEY 0x0b18 359*4882a593Smuzhiyun #define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c 360*4882a593Smuzhiyun #define EN_IP_PERI_SECURE_TOP_RTC 0x0b20 361*4882a593Smuzhiyun #define EN_IP_PERI_SECURE_TZPC 0x0b24 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun /* 364*4882a593Smuzhiyun *Registers for CMU_TOP 365*4882a593Smuzhiyun */ 366*4882a593Smuzhiyun #define DISP_PLL_LOCK 0x0000 367*4882a593Smuzhiyun #define AUD_PLL_LOCK 0x0004 368*4882a593Smuzhiyun #define DISP_PLL_CON0 0x0100 369*4882a593Smuzhiyun #define DISP_PLL_CON1 0x0104 370*4882a593Smuzhiyun #define DISP_PLL_FDET 0x0108 371*4882a593Smuzhiyun #define AUD_PLL_CON0 0x0110 372*4882a593Smuzhiyun #define AUD_PLL_CON1 0x0114 373*4882a593Smuzhiyun #define AUD_PLL_CON2 0x0118 374*4882a593Smuzhiyun #define AUD_PLL_FDET 0x011c 375*4882a593Smuzhiyun #define MUX_SEL_TOP_PLL0 0x0200 376*4882a593Smuzhiyun #define MUX_SEL_TOP_MFC 0x0204 377*4882a593Smuzhiyun #define MUX_SEL_TOP_G2D 0x0208 378*4882a593Smuzhiyun #define MUX_SEL_TOP_GSCL 0x020c 379*4882a593Smuzhiyun #define MUX_SEL_TOP_ISP10 0x0214 380*4882a593Smuzhiyun #define MUX_SEL_TOP_ISP11 0x0218 381*4882a593Smuzhiyun #define MUX_SEL_TOP_DISP0 0x021c 382*4882a593Smuzhiyun #define MUX_SEL_TOP_DISP1 0x0220 383*4882a593Smuzhiyun #define MUX_SEL_TOP_BUS 0x0224 384*4882a593Smuzhiyun #define MUX_SEL_TOP_PERI0 0x0228 385*4882a593Smuzhiyun #define MUX_SEL_TOP_PERI1 0x022c 386*4882a593Smuzhiyun #define MUX_SEL_TOP_FSYS 0x0230 387*4882a593Smuzhiyun #define MUX_ENABLE_TOP_PLL0 0x0300 388*4882a593Smuzhiyun #define MUX_ENABLE_TOP_MFC 0x0304 389*4882a593Smuzhiyun #define MUX_ENABLE_TOP_G2D 0x0308 390*4882a593Smuzhiyun #define MUX_ENABLE_TOP_GSCL 0x030c 391*4882a593Smuzhiyun #define MUX_ENABLE_TOP_ISP10 0x0314 392*4882a593Smuzhiyun #define MUX_ENABLE_TOP_ISP11 0x0318 393*4882a593Smuzhiyun #define MUX_ENABLE_TOP_DISP0 0x031c 394*4882a593Smuzhiyun #define MUX_ENABLE_TOP_DISP1 0x0320 395*4882a593Smuzhiyun #define MUX_ENABLE_TOP_BUS 0x0324 396*4882a593Smuzhiyun #define MUX_ENABLE_TOP_PERI0 0x0328 397*4882a593Smuzhiyun #define MUX_ENABLE_TOP_PERI1 0x032c 398*4882a593Smuzhiyun #define MUX_ENABLE_TOP_FSYS 0x0330 399*4882a593Smuzhiyun #define MUX_STAT_TOP_PLL0 0x0400 400*4882a593Smuzhiyun #define MUX_STAT_TOP_MFC 0x0404 401*4882a593Smuzhiyun #define MUX_STAT_TOP_G2D 0x0408 402*4882a593Smuzhiyun #define MUX_STAT_TOP_GSCL 0x040c 403*4882a593Smuzhiyun #define MUX_STAT_TOP_ISP10 0x0414 404*4882a593Smuzhiyun #define MUX_STAT_TOP_ISP11 0x0418 405*4882a593Smuzhiyun #define MUX_STAT_TOP_DISP0 0x041c 406*4882a593Smuzhiyun #define MUX_STAT_TOP_DISP1 0x0420 407*4882a593Smuzhiyun #define MUX_STAT_TOP_BUS 0x0424 408*4882a593Smuzhiyun #define MUX_STAT_TOP_PERI0 0x0428 409*4882a593Smuzhiyun #define MUX_STAT_TOP_PERI1 0x042c 410*4882a593Smuzhiyun #define MUX_STAT_TOP_FSYS 0x0430 411*4882a593Smuzhiyun #define MUX_IGNORE_TOP_PLL0 0x0500 412*4882a593Smuzhiyun #define MUX_IGNORE_TOP_MFC 0x0504 413*4882a593Smuzhiyun #define MUX_IGNORE_TOP_G2D 0x0508 414*4882a593Smuzhiyun #define MUX_IGNORE_TOP_GSCL 0x050c 415*4882a593Smuzhiyun #define MUX_IGNORE_TOP_ISP10 0x0514 416*4882a593Smuzhiyun #define MUX_IGNORE_TOP_ISP11 0x0518 417*4882a593Smuzhiyun #define MUX_IGNORE_TOP_DISP0 0x051c 418*4882a593Smuzhiyun #define MUX_IGNORE_TOP_DISP1 0x0520 419*4882a593Smuzhiyun #define MUX_IGNORE_TOP_BUS 0x0524 420*4882a593Smuzhiyun #define MUX_IGNORE_TOP_PERI0 0x0528 421*4882a593Smuzhiyun #define MUX_IGNORE_TOP_PERI1 0x052c 422*4882a593Smuzhiyun #define MUX_IGNORE_TOP_FSYS 0x0530 423*4882a593Smuzhiyun #define DIV_TOP_G2D_MFC 0x0600 424*4882a593Smuzhiyun #define DIV_TOP_GSCL_ISP0 0x0604 425*4882a593Smuzhiyun #define DIV_TOP_ISP10 0x0608 426*4882a593Smuzhiyun #define DIV_TOP_ISP11 0x060c 427*4882a593Smuzhiyun #define DIV_TOP_DISP 0x0610 428*4882a593Smuzhiyun #define DIV_TOP_BUS 0x0614 429*4882a593Smuzhiyun #define DIV_TOP_PERI0 0x0618 430*4882a593Smuzhiyun #define DIV_TOP_PERI1 0x061c 431*4882a593Smuzhiyun #define DIV_TOP_PERI2 0x0620 432*4882a593Smuzhiyun #define DIV_TOP_FSYS0 0x0624 433*4882a593Smuzhiyun #define DIV_TOP_FSYS1 0x0628 434*4882a593Smuzhiyun #define DIV_TOP_HPM 0x062c 435*4882a593Smuzhiyun #define DIV_TOP_PLL_FDET 0x0630 436*4882a593Smuzhiyun #define DIV_STAT_TOP_G2D_MFC 0x0700 437*4882a593Smuzhiyun #define DIV_STAT_TOP_GSCL_ISP0 0x0704 438*4882a593Smuzhiyun #define DIV_STAT_TOP_ISP10 0x0708 439*4882a593Smuzhiyun #define DIV_STAT_TOP_ISP11 0x070c 440*4882a593Smuzhiyun #define DIV_STAT_TOP_DISP 0x0710 441*4882a593Smuzhiyun #define DIV_STAT_TOP_BUS 0x0714 442*4882a593Smuzhiyun #define DIV_STAT_TOP_PERI0 0x0718 443*4882a593Smuzhiyun #define DIV_STAT_TOP_PERI1 0x071c 444*4882a593Smuzhiyun #define DIV_STAT_TOP_PERI2 0x0720 445*4882a593Smuzhiyun #define DIV_STAT_TOP_FSYS0 0x0724 446*4882a593Smuzhiyun #define DIV_STAT_TOP_FSYS1 0x0728 447*4882a593Smuzhiyun #define DIV_STAT_TOP_HPM 0x072c 448*4882a593Smuzhiyun #define DIV_STAT_TOP_PLL_FDET 0x0730 449*4882a593Smuzhiyun #define EN_ACLK_TOP 0x0800 450*4882a593Smuzhiyun #define EN_SCLK_TOP 0x0a00 451*4882a593Smuzhiyun #define EN_IP_TOP 0x0b00 452*4882a593Smuzhiyun #define CLKOUT_CMU_TOP 0x0c00 453*4882a593Smuzhiyun #define CLKOUT_CMU_TOP_DIV_STAT 0x0c04 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #endif /*__CLK_EXYNOS5260_H */ 456*4882a593Smuzhiyun 457