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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mssr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14 and MSSR (Module Standby and Software Reset) blocks are intimately connected,
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
27 - renesas,r7s9210-cpg-mssr # RZ/A2
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o
5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
[all …]
H A Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
48 * These are NOT valid for R-Car Gen1 and RZ/A1!
[all …]
H A Dr7s9210-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on r8a7795-cpg-mssr.c
13 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
16 #include "renesas-cpg-mssr.h"
169 parent = clks[core->parent]; in rza2_cpg_clk_register()
173 switch (core->id) { in rza2_cpg_clk_register()
185 return ERR_PTR(-EINVAL); in rza2_cpg_clk_register()
188 if (core->id == CLK_MAIN) in rza2_cpg_clk_register()
191 return clk_register_fixed_factor(NULL, core->name, in rza2_cpg_clk_register()
[all …]
H A Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
124 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
125 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
126 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
127 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
[all …]
H A Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
127 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
128 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
137 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
138 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
[all …]
H A Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
126 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
[all …]
H A Dr8a779a0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/rcar-rst.h>
26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
28 #include "renesas-cpg-mssr.h"
172 parent = clks[core->parent & 0xffff]; /* some types use high bits */ in rcar_r8a779a0_cpg_clk_register()
176 switch (core->type) { in rcar_r8a779a0_cpg_clk_register()
178 div = cpg_pll_config->extal_div; in rcar_r8a779a0_cpg_clk_register()
182 mult = cpg_pll_config->pll1_mult; in rcar_r8a779a0_cpg_clk_register()
[all …]
H A Drenesas-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Definitions of CPG Core Clocks
15 * - Clock outputs exported to DT
16 * - External input clocks
17 * - Internal CPG clocks
70 /* Convert from sparse base-100 to packed index space */
71 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
78 /* Convert from sparse base-10 to packed index space */
95 * SoC-specific CPG/MSSR Description
114 * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
[all …]
H A Dr8a7796-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
6 * Copyright (C) 2016-2019 Glider bvba
7 * Copyright (C) 2018-2019 Renesas Electronics Corp.
9 * Based on r8a7795-cpg-mssr.c
19 #include <linux/soc/renesas/rcar-rst.h>
21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen3-cpg.h"
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
[all …]
H A Dr8a77990-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
136 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
137 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
138 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
[all …]
H A Dr8a774c0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a77990-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
140 DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1),
141 DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1),
142 DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1),
153 DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1),
[all …]
H A Dr8a7791-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Glider bvba
7 * Based on clk-rcar-gen2.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen2-cpg.h"
96 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
97 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
98 DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
[all …]
H A Dr8a7743-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/soc/renesas/rcar-rst.h>
14 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
16 #include "renesas-cpg-mssr.h"
17 #include "rcar-gen2-cpg.h"
86 DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
87 DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
88 DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
104 DEF_MOD("sys-dmac1", 218, R8A7743_CLK_ZS),
105 DEF_MOD("sys-dmac0", 219, R8A7743_CLK_ZS),
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-shmobile/
H A Dsetup-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 support
12 #include <linux/dma-map-ops.h>
24 #include "rcar-gen2.h"
27 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
32 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drenesas,vsp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
20 - renesas,vsp1 # R-Car Gen2 and RZ/G1
21 - renesas,vsp2 # R-Car Gen3 and RZ/G2
32 power-domains:
44 - compatible
[all …]
H A Drenesas,vin.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Video Input (VIN)
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car Video Input (VIN) device provides video input capabilities for the
15 Renesas R-Car family of devices.
20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
25 - items:
26 - enum:
[all …]
H A Drenesas,fdp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Fine Display Processor (FDP1)
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The FDP1 is a de-interlacing module which converts interlaced video to
21 - renesas,fdp1
32 power-domains:
42 Not allowed on R-Car Gen2, mandatory on R-Car Gen3.
45 - compatible
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/
H A Dr8a779a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a76";
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car LVDS Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21 - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr7s9210.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
23 clock-frequency = <0>;
27 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dr7s9210-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/renesas-cpg-mssr.h>
12 /* R7S9210 CPG Core Clocks */
H A Dr8a7795-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* r8a7795 CPG Core Clocks */
59 /* r8a7795 ES2.0 CPG Core Clocks */
/OK3568_Linux_fs/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c2 * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <clk-uclass.h>
21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
33 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
34 * R-Car Gen2, R-Car Gen3, and RZ/G1.
35 * These are NOT valid for R-Car Gen1 and RZ/A1!
63 #define RMSTPCR(i) (smstpcr[i] - 0x20)
83 * Definitions of CPG Core Clocks
[all …]
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Dr8a7795-cpg-mssr.h12 #include <dt-bindings/clock/renesas-cpg-mssr.h>
14 /* r8a7795 CPG Core Clocks */
63 /* r8a7795 ES2.0 CPG Core Clocks */

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