1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/renesas,vsp1.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas VSP Video Processing Engine 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun The VSP is a video processing engine that supports up-/down-scaling, alpha 14*4882a593Smuzhiyun blending, color space conversion and various other image processing features. 15*4882a593Smuzhiyun It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun enum: 20*4882a593Smuzhiyun - renesas,vsp1 # R-Car Gen2 and RZ/G1 21*4882a593Smuzhiyun - renesas,vsp2 # R-Car Gen3 and RZ/G2 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun interrupts: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clocks: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun power-domains: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun resets: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun renesas,fcp: 39*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle 40*4882a593Smuzhiyun description: 41*4882a593Smuzhiyun A phandle referencing the FCP that handles memory accesses for the VSP. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunrequired: 44*4882a593Smuzhiyun - compatible 45*4882a593Smuzhiyun - reg 46*4882a593Smuzhiyun - interrupts 47*4882a593Smuzhiyun - clocks 48*4882a593Smuzhiyun - power-domains 49*4882a593Smuzhiyun - resets 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunadditionalProperties: false 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunif: 54*4882a593Smuzhiyun properties: 55*4882a593Smuzhiyun compatible: 56*4882a593Smuzhiyun items: 57*4882a593Smuzhiyun - const: renesas,vsp1 58*4882a593Smuzhiyunthen: 59*4882a593Smuzhiyun properties: 60*4882a593Smuzhiyun renesas,fcp: false 61*4882a593Smuzhiyunelse: 62*4882a593Smuzhiyun required: 63*4882a593Smuzhiyun - renesas,fcp 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunexamples: 66*4882a593Smuzhiyun # R8A7790 (R-Car H2) VSP1-S 67*4882a593Smuzhiyun - | 68*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 69*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 70*4882a593Smuzhiyun #include <dt-bindings/power/r8a7790-sysc.h> 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun vsp@fe928000 { 73*4882a593Smuzhiyun compatible = "renesas,vsp1"; 74*4882a593Smuzhiyun reg = <0xfe928000 0x8000>; 75*4882a593Smuzhiyun interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 76*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 131>; 77*4882a593Smuzhiyun power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 78*4882a593Smuzhiyun resets = <&cpg 131>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun # R8A77951 (R-Car H3) VSP2-BC 82*4882a593Smuzhiyun - | 83*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 84*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 85*4882a593Smuzhiyun #include <dt-bindings/power/r8a7795-sysc.h> 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun vsp@fe920000 { 88*4882a593Smuzhiyun compatible = "renesas,vsp2"; 89*4882a593Smuzhiyun reg = <0xfe920000 0x8000>; 90*4882a593Smuzhiyun interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 91*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 624>; 92*4882a593Smuzhiyun power-domains = <&sysc R8A7795_PD_A3VP>; 93*4882a593Smuzhiyun resets = <&cpg 624>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun renesas,fcp = <&fcpvb1>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun... 98