clk/renesas/r8a779a0-cpg-mssr.c

1 // SPDX-License-Identifier: GPL-2.0
7  * Based on r8a7795-cpg-mssr.c
16 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/rcar-rst.h>
26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
28 #include "renesas-cpg-mssr.h"
172 	parent = clks[core->parent & 0xffff];	/* some types use high bits */  in rcar_r8a779a0_cpg_clk_register()
176 	switch (core->type) {  in rcar_r8a779a0_cpg_clk_register()
178 		div = cpg_pll_config->extal_div;  in rcar_r8a779a0_cpg_clk_register()
182 		mult = cpg_pll_config->pll1_mult;  in rcar_r8a779a0_cpg_clk_register()
183 		div = cpg_pll_config->pll1_div;  in rcar_r8a779a0_cpg_clk_register()
187 		value = readl(base + core->offset);  in rcar_r8a779a0_cpg_clk_register()
192 		mult = cpg_pll_config->pll5_mult;  in rcar_r8a779a0_cpg_clk_register()
193 		div = cpg_pll_config->pll5_div;  in rcar_r8a779a0_cpg_clk_register()
201 		if (cpg_mode & BIT(core->offset)) {  in rcar_r8a779a0_cpg_clk_register()
202 			div = core->div & 0xffff;  in rcar_r8a779a0_cpg_clk_register()
204 			parent = clks[core->parent >> 16];  in rcar_r8a779a0_cpg_clk_register()
207 			div = core->div >> 16;  in rcar_r8a779a0_cpg_clk_register()
216 		div = cpg_pll_config->osc_prediv * core->div;  in rcar_r8a779a0_cpg_clk_register()
220 		return ERR_PTR(-EINVAL);  in rcar_r8a779a0_cpg_clk_register()
223 	return clk_register_fixed_factor(NULL, core->name,  in rcar_r8a779a0_cpg_clk_register()
228  * CPG Clock Data
233  * --------------------------------------------------------