1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* R7S9210 CPG Core Clocks */ 13*4882a593Smuzhiyun #define R7S9210_CLK_I 0 14*4882a593Smuzhiyun #define R7S9210_CLK_G 1 15*4882a593Smuzhiyun #define R7S9210_CLK_B 2 16*4882a593Smuzhiyun #define R7S9210_CLK_P1 3 17*4882a593Smuzhiyun #define R7S9210_CLK_P1C 4 18*4882a593Smuzhiyun #define R7S9210_CLK_P0 5 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ 21