Merge changes from topic "sve+amu" into integration

* changes:
fix(plat/tc0): enable AMU extension
fix(el3_runtime): fix SVE and AMU extension enablement flags

Merge "docs(maintainers): update imx8 entry" into integration

Merge "refactor(aarch64): remove `FEAT_BTI` architecture check" into integration

docs(maintainers): update imx8 entry

Add myself as i.MX8 maintainer.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58

Merge changes from topic "diphda" into integration

* changes:
feat: disabling non volatile counters in diphda
feat: adding the diphda platform

fix(sdei): set SPSR for SDEI based on TakeException

The SDEI specification now says that during an SDEI
event handler dispatch the SPSR should be set according
to the TakeException() pseudocode func

fix(sdei): set SPSR for SDEI based on TakeException

The SDEI specification now says that during an SDEI
event handler dispatch the SPSR should be set according
to the TakeException() pseudocode function defined in
the Arm Architecture Reference Manual. This patch sets
the SPSR according to the function given in
ARM DDI 0487F.c page J1-7635

Change-Id: Id2f8f2464fd69c701d81626162827e5c4449b658
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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fix(plat/tc0): enable AMU extension

Recent changes to enable SVE for the secure world have disabled AMU
extension by default in the reset value of CPTR_EL3 register. So the
platform has to enable th

fix(plat/tc0): enable AMU extension

Recent changes to enable SVE for the secure world have disabled AMU
extension by default in the reset value of CPTR_EL3 register. So the
platform has to enable this extension explicitly.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I7d930d96ec22d7c3db961411370564bece0ce272

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fix(el3_runtime): fix SVE and AMU extension enablement flags

If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon e

fix(el3_runtime): fix SVE and AMU extension enablement flags

If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087

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fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif

A RAS error may be triggered while offline core in OS. Error:
Uncorrected software error in the Distributor, with IERR=9,SERR=f

fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif

A RAS error may be triggered while offline core in OS. Error:
Uncorrected software error in the Distributor, with IERR=9,SERR=f.
Core put to sleep before its Group enables were cleared.

gicv3_cpuif_disable() will be called in offline core flow.
According to GIC architecture version 3 and version 4:
Architectural execution of a DSB instruction guarantees that
the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1,
ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed
by the associated Redistributor.
An ISB or other context synchronization operation must precede
the DSB to ensure visibility of System register writes.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d

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refactor(plat/allwinner): clean up platform definitions

Group the SCP base/size definitions in a more logical location.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id43f9b468d7d8

refactor(plat/allwinner): clean up platform definitions

Group the SCP base/size definitions in a more logical location.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id43f9b468d7d855a2413173d674a5ee666527808

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refactor(plat/allwinner): do not map BL32 DRAM at EL3

BL31 does not appear to ever access the DRAM allocated to BL32,
so there is no need to map it at EL3.

Signed-off-by: Samuel Holland <samuel@sho

refactor(plat/allwinner): do not map BL32 DRAM at EL3

BL31 does not appear to ever access the DRAM allocated to BL32,
so there is no need to map it at EL3.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie8727b793e53ea14517894942266f6da0333eb74

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refactor(plat/allwinner): map SRAM as device memory by default

The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by defaul

refactor(plat/allwinner): map SRAM as device memory by default

The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by default.
This scheme requires carveouts and cache maintenance code for proper
synchronization with the coprocessor.

A better scheme is to only map pages owned by BL31 as normal memory,
and leave everything else as device memory. This removes the need for
cache maintenance, and it makes the mapping for BL31 RW data explicit
instead of magic.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348

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refactor(plat/allwinner): rename static mmap region constant

This constant specifically refers to the number of static mmap regions.
Rename it to make that clear.

Signed-off-by: Samuel Holland <sam

refactor(plat/allwinner): rename static mmap region constant

This constant specifically refers to the number of static mmap regions.
Rename it to make that clear.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I475c037777ce2a10db2631ec0e7446bb73590a36

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feat(bl_common): import BL_NOBITS_{BASE,END} when defined

If SEPARATE_NOBITS_REGION is enabled, the platform may need to map
memory specifically for that region. Import the symbols from the linker
s

feat(bl_common): import BL_NOBITS_{BASE,END} when defined

If SEPARATE_NOBITS_REGION is enabled, the platform may need to map
memory specifically for that region. Import the symbols from the linker
script to allow the platform to do so.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iaec4dee94a6735b22f58f7b61f18d53e7bc6ca8d

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feat: disabling non volatile counters in diphda

At this stage of development Non Volatile counters are not implemented
in the Diphda platform.

This commit disables their use during the Trusted Boar

feat: disabling non volatile counters in diphda

At this stage of development Non Volatile counters are not implemented
in the Diphda platform.

This commit disables their use during the Trusted Board Boot by
overriding the NV counters get/set functions.

Change-Id: I8dcbebe0281cc4d0837c283ff637e20b850988ef
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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feat: adding the diphda platform

This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.

Diphda uses a FIP image located in the flash. The FIP contain

feat: adding the diphda platform

This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.

Diphda uses a FIP image located in the flash. The FIP contains the
following components:

- BL2
- BL31
- BL32
- BL32 SPMC manifest
- BL33
- The TBB certificates

The board boot relies on CoT (chain of trust). The trusted-firmware-a
BL2 is extracted from the FIP and verified by the Secure Enclave
processor. BL2 verification relies on the signature area at the
beginning of the BL2 image. This area is needed by the SecureEnclave
bootloader.

Then, the application processor is released from reset and starts by
executing BL2.

BL2 performs the actions described in the trusted-firmware-a TBB design
document.

Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d

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Merge "fix(mediatek/mt8192/spm): add missing bit define for debug purpose" into integration

Merge changes from topic "scmi-power" into integration

* changes:
fix(drivers/scmi-msg): entry: add weak functions
feat(drivers/scmi-msg): add power domain protocol
fix(drivers/scmi-msg): smt:

Merge changes from topic "scmi-power" into integration

* changes:
fix(drivers/scmi-msg): entry: add weak functions
feat(drivers/scmi-msg): add power domain protocol
fix(drivers/scmi-msg): smt: fix build for aarch64

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feat(ff-a): change manifest messaging method

Align documentation with changes of messaging method for partition
manifest:
- Bit[0]: support for receiving direct message requests
- Bit[1]

feat(ff-a): change manifest messaging method

Align documentation with changes of messaging method for partition
manifest:
- Bit[0]: support for receiving direct message requests
- Bit[1]: support for sending direct messages
- Bit[2]: support for indirect messaging
- Bit[3]: support for managed exit
Change the optee_sp_manifest to align with the new messaging method
description.

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: I333e82c546c03698c95f0c77293018f8dca5ba9c

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fix(drivers/scmi-msg): entry: add weak functions

One platform may not implement all the protocols, to avoid build break
when we not include all the protocols, add weak functions.

Reviewed-by: Jacky

fix(drivers/scmi-msg): entry: add weak functions

One platform may not implement all the protocols, to avoid build break
when we not include all the protocols, add weak functions.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I1485baa2e8f381cb0eede1a7b93ed10e49934971

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feat(drivers/scmi-msg): add power domain protocol

Add SCMI power domain protocol, with POWER_STATE_NOTIFY and
POWER_STATE_CHANGE_REQUESTED_NOTIFY not implemented.

Reviewed-by: Jacky Bai <ping.bai@n

feat(drivers/scmi-msg): add power domain protocol

Add SCMI power domain protocol, with POWER_STATE_NOTIFY and
POWER_STATE_CHANGE_REQUESTED_NOTIFY not implemented.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ia7c4db57c4c702667f8eaa630c924016e4a8bde0

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feat(plat/versal): add support for SLS mitigation

This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerabili

feat(plat/versal): add support for SLS mitigation

This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2

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fix(mediatek/mt8192/spm): add missing bit define for debug purpose

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6dbf6d4ea6310c3371ca15d1e7cce249a05af2fb

feat(common/debug): add new macro ERROR_NL() to print just a newline

Existing macro ERROR() prints string "ERROR" followed by string
specified by caller. Therefore via this existing macro it is not

feat(common/debug): add new macro ERROR_NL() to print just a newline

Existing macro ERROR() prints string "ERROR" followed by string
specified by caller. Therefore via this existing macro it is not
possible to end incomplete / existing line by a newline character.

This change adds a new macro ERROR_NL() which prints just a newline
character without any prefix. Implementation of this macro is done via a
new function tf_log_newline() which based on supplied log level either
return or print newline character.

If needed in future based on this tf_log_newline() function can be
defined also macros for other log levels.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I05414ca177f94cdc0f6077394d9c4af4a4382306

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feat(plat/imx/imx8m/imx8mm): enlarge BL33 (U-boot) size in FIP

When enabling U-boot with UEFI and secure boot, the size of U-boot
becomes more than 1MB. So we enlarge BL33 to 2MB.

Signed-off-by: Yi

feat(plat/imx/imx8m/imx8mm): enlarge BL33 (U-boot) size in FIP

When enabling U-boot with UEFI and secure boot, the size of U-boot
becomes more than 1MB. So we enlarge BL33 to 2MB.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I9d9d24132bb1ec17ef6080dc72e93c7f531c97b5

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