1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 #include <plat_marvell.h> 18 19 #include "phy-comphy-3700.h" 20 #include "phy-comphy-common.h" 21 22 /* 23 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 24 * Linux is up to 0x178 so none will access it from Linux in runtime 25 * concurrently. 26 */ 27 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 28 29 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 30 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 31 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 32 33 struct sgmii_phy_init_data_fix { 34 uint16_t addr; 35 uint16_t value; 36 }; 37 38 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 39 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 40 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 41 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 42 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 43 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 44 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 45 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 46 {0x104, 0x0C10} 47 }; 48 49 /* 40M1G25 mode init data */ 50 static uint16_t sgmii_phy_init[512] = { 51 /* 0 1 2 3 4 5 6 7 */ 52 /*-----------------------------------------------------------*/ 53 /* 8 9 A B C D E F */ 54 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 55 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 56 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 57 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 58 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 59 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 60 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 61 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 62 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 63 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 64 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 65 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 66 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 67 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 68 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 69 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 70 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 71 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 72 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 73 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 74 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 75 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 77 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 78 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 79 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 80 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 81 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 82 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 83 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 84 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 85 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 86 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 88 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 101 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 118 }; 119 120 /* PHY selector configures with corresponding modes */ 121 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 122 uint32_t comphy_mode) 123 { 124 uint32_t reg; 125 int mode = COMPHY_GET_MODE(comphy_mode); 126 127 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 128 switch (mode) { 129 case (COMPHY_SATA_MODE): 130 /* SATA must be in Lane2 */ 131 if (comphy_index == COMPHY_LANE2) 132 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 133 else 134 goto error; 135 break; 136 137 case (COMPHY_SGMII_MODE): 138 case (COMPHY_2500BASEX_MODE): 139 if (comphy_index == COMPHY_LANE0) 140 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 141 else if (comphy_index == COMPHY_LANE1) 142 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 143 else 144 goto error; 145 break; 146 147 case (COMPHY_USB3H_MODE): 148 case (COMPHY_USB3D_MODE): 149 case (COMPHY_USB3_MODE): 150 if (comphy_index == COMPHY_LANE2) 151 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 152 else if (comphy_index == COMPHY_LANE0) 153 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 154 else 155 goto error; 156 break; 157 158 case (COMPHY_PCIE_MODE): 159 /* PCIE must be in Lane1 */ 160 if (comphy_index == COMPHY_LANE1) 161 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 162 else 163 goto error; 164 break; 165 166 default: 167 goto error; 168 } 169 170 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 171 return; 172 error: 173 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 174 } 175 176 /* 177 * This is something like the inverse of the previous function: for given 178 * lane it returns COMPHY_*_MODE. 179 * 180 * It is useful when powering the phy off. 181 * 182 * This function returns COMPHY_USB3_MODE even if the phy was configured 183 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization 184 * code does not differentiate between these modes.) 185 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with 186 * COMPHY_2500BASEX_MODE. (The sgmii phy initialization code does differentiate 187 * between these modes, but it is irrelevant when powering the phy off.) 188 */ 189 static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index) 190 { 191 uint32_t reg; 192 193 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 194 switch (comphy_index) { 195 case COMPHY_LANE0: 196 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0) 197 return COMPHY_USB3_MODE; 198 else 199 return COMPHY_SGMII_MODE; 200 case COMPHY_LANE1: 201 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0) 202 return COMPHY_PCIE_MODE; 203 else 204 return COMPHY_SGMII_MODE; 205 case COMPHY_LANE2: 206 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0) 207 return COMPHY_USB3_MODE; 208 else 209 return COMPHY_SATA_MODE; 210 } 211 212 return COMPHY_UNUSED; 213 } 214 215 /* It is only used for SATA and USB3 on comphy lane2. */ 216 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 217 uint16_t mask, bool is_sata) 218 { 219 /* 220 * When Lane 2 PHY is for USB3, access the PHY registers 221 * through indirect Address and Data registers: 222 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 223 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 224 * within the SATA Host Controller registers, Lane 2 base register 225 * offset is 0x200 226 */ 227 if (is_sata) { 228 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 229 } else { 230 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 231 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 232 } 233 234 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 235 } 236 237 /* It is only used for SATA on comphy lane2. */ 238 static void comphy_sata_set_indirect(uintptr_t addr, uint32_t reg_offset, 239 uint16_t data, uint16_t mask) 240 { 241 comphy_set_indirect(addr, reg_offset, data, mask, true); 242 } 243 244 /* It is only used for USB3 indirect access on comphy lane2. */ 245 static void comphy_usb3_set_indirect(uintptr_t addr, uint32_t reg_offset, 246 uint16_t data, uint16_t mask) 247 { 248 comphy_set_indirect(addr, reg_offset, data, mask, false); 249 } 250 251 /* It is only used for USB3 direct access not on comphy lane2. */ 252 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 253 uint16_t data, uint16_t mask) 254 { 255 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 256 } 257 258 static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode, 259 uintptr_t sd_ip_addr) 260 { 261 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 262 int addr, fix_idx; 263 uint16_t val; 264 265 fix_idx = 0; 266 for (addr = 0; addr < 512; addr++) { 267 /* 268 * All PHY register values are defined in full for 3.125Gbps 269 * SERDES speed. The values required for 1.25 Gbps are almost 270 * the same and only few registers should be "fixed" in 271 * comparison to 3.125 Gbps values. These register values are 272 * stored in "sgmii_phy_init_fix" array. 273 */ 274 if ((mode != COMPHY_SGMII_MODE) && 275 (sgmii_phy_init_fix[fix_idx].addr == addr)) { 276 /* Use new value */ 277 val = sgmii_phy_init_fix[fix_idx].value; 278 if (fix_idx < fix_arr_sz) 279 fix_idx++; 280 } else { 281 val = sgmii_phy_init[addr]; 282 } 283 284 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 285 } 286 } 287 288 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 289 uint32_t comphy_mode) 290 { 291 int ret = 0; 292 uint32_t offset, data = 0, ref_clk; 293 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 294 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 295 296 debug_enter(); 297 298 /* Configure phy selector for SATA */ 299 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 300 301 /* Clear phy isolation mode to make it work in normal mode */ 302 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 303 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE); 304 305 /* 0. Check the Polarity invert bits */ 306 if (invert & COMPHY_POLARITY_TXD_INVERT) 307 data |= TXD_INVERT_BIT; 308 if (invert & COMPHY_POLARITY_RXD_INVERT) 309 data |= RXD_INVERT_BIT; 310 311 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 312 comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 313 RXD_INVERT_BIT); 314 315 /* 1. Select 40-bit data width width */ 316 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; 317 comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 318 SEL_DATA_WIDTH_MASK); 319 320 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 321 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 322 if (get_ref_clk() == 40) 323 ref_clk = REF_CLOCK_SPEED_40M; 324 else 325 ref_clk = REF_CLOCK_SPEED_25M; 326 327 comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 328 REF_FREF_SEL_MASK | PHY_MODE_MASK); 329 330 /* 3. Use maximum PLL rate (no power save) */ 331 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 332 comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 333 USE_MAX_PLL_RATE_BIT); 334 335 /* 4. Reset reserved bit */ 336 comphy_sata_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 337 PHYCTRL_FRM_PIN_BIT); 338 339 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 340 /* XXX: in U-Boot below sequence was executed in this place, in Linux 341 * not. Now it is done only in U-Boot before this comphy 342 * initialization - tests shows that it works ok, but in case of any 343 * future problem it is left for reference. 344 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 345 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 346 */ 347 348 /* Wait for > 55 us to allow PLL be enabled */ 349 udelay(PLL_SET_DELAY_US); 350 351 /* Polling status */ 352 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 353 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 354 355 ret = polling_with_timeout(comphy_indir_regs + 356 COMPHY_LANE2_INDIR_DATA_OFFSET, 357 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 358 COMPHY_PLL_TIMEOUT, REG_32BIT); 359 360 debug_exit(); 361 362 return ret; 363 } 364 365 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 366 uint32_t comphy_mode) 367 { 368 int ret = 0; 369 uint32_t mask, data, offset; 370 uintptr_t sd_ip_addr; 371 int mode = COMPHY_GET_MODE(comphy_mode); 372 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 373 374 debug_enter(); 375 376 /* Set selector */ 377 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 378 379 /* Serdes IP Base address 380 * COMPHY Lane0 -- USB3/GBE1 381 * COMPHY Lane1 -- PCIe/GBE0 382 */ 383 if (comphy_index == COMPHY_LANE0) { 384 /* Get usb3 and gbe */ 385 sd_ip_addr = USB3_GBE1_PHY; 386 } else 387 sd_ip_addr = COMPHY_SD_ADDR; 388 389 /* 390 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 391 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 392 * PHY TXP/TXN output to idle state during PHY initialization 393 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 394 */ 395 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 396 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 397 PIN_PU_TX_BIT; 398 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 399 reg_set(offset, data, mask); 400 401 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 402 data = 0; 403 mask = PIN_RESET_COMPHY_BIT; 404 reg_set(offset, data, mask); 405 406 /* 407 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 408 * bit rate 409 */ 410 if (mode == COMPHY_SGMII_MODE) { 411 /* SGMII 1G, SerDes speed 1.25G */ 412 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 413 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 414 } else if (mode == COMPHY_2500BASEX_MODE) { 415 /* 2500Base-X, SerDes speed 3.125G */ 416 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; 417 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; 418 } else { 419 /* Other rates are not supported */ 420 ERROR("unsupported SGMII speed on comphy lane%d\n", 421 comphy_index); 422 return -EINVAL; 423 } 424 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 425 reg_set(offset, data, mask); 426 427 /* 428 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 429 * start SW programming. 430 */ 431 mdelay(10); 432 433 /* 7. Program COMPHY register PHY_MODE */ 434 data = PHY_MODE_SGMII; 435 mask = PHY_MODE_MASK; 436 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 437 438 /* 439 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 440 * source 441 */ 442 data = 0; 443 mask = PHY_REF_CLK_SEL; 444 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); 445 446 /* 447 * 9. Set correct reference clock frequency in COMPHY register 448 * REF_FREF_SEL. 449 */ 450 if (get_ref_clk() == 40) 451 data = REF_CLOCK_SPEED_50M; 452 else 453 data = REF_CLOCK_SPEED_25M; 454 455 mask = REF_FREF_SEL_MASK; 456 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 457 458 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 459 * This step is mentioned in the flow received from verification team. 460 * However the PHY_GEN_MAX value is only meaningful for other interfaces 461 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 462 * speed 2.5/5 Gbps 463 */ 464 465 /* 466 * 11. Program COMPHY register SEL_BITS to set correct parallel data 467 * bus width 468 */ 469 data = DATA_WIDTH_10BIT; 470 mask = SEL_DATA_WIDTH_MASK; 471 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); 472 473 /* 474 * 12. As long as DFE function needs to be enabled in any mode, 475 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 476 * for real chip during COMPHY power on. 477 * The step 14 exists (and empty) in the original initialization flow 478 * obtained from the verification team. According to the functional 479 * specification DFE_UPDATE_EN already has the default value 0x3F 480 */ 481 482 /* 483 * 13. Program COMPHY GEN registers. 484 * These registers should be programmed based on the lab testing result 485 * to achieve optimal performance. Please contact the CEA group to get 486 * the related GEN table during real chip bring-up. We only required to 487 * run though the entire registers programming flow defined by 488 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 489 * 25 MHz the default values stored in PHY registers are OK. 490 */ 491 debug("Running C-DPI phy init %s mode\n", 492 mode == COMPHY_2500BASEX_MODE ? "2G5" : "1G"); 493 if (get_ref_clk() == 40) 494 comphy_sgmii_phy_init(comphy_index, mode, sd_ip_addr); 495 496 /* 497 * 14. [Simulation Only] should not be used for real chip. 498 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 499 * (R02h[9]) to 1 to shorten COMPHY simulation time. 500 */ 501 502 /* 503 * 15. [Simulation Only: should not be used for real chip] 504 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 505 * simulation time. 506 */ 507 508 /* 509 * 16. Check the PHY Polarity invert bit 510 */ 511 data = 0x0; 512 if (invert & COMPHY_POLARITY_TXD_INVERT) 513 data |= TXD_INVERT_BIT; 514 if (invert & COMPHY_POLARITY_RXD_INVERT) 515 data |= RXD_INVERT_BIT; 516 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 517 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask); 518 519 /* 520 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 521 * start PHY power up sequence. All the PHY register programming should 522 * be done before PIN_PU_PLL=1. There should be no register programming 523 * for normal PHY operation from this point. 524 */ 525 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 526 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 527 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 528 529 /* 530 * 18. Wait for PHY power up sequence to finish by checking output ports 531 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 532 */ 533 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 534 COMPHY_PHY_STATUS_OFFSET(comphy_index), 535 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 536 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 537 COMPHY_PLL_TIMEOUT, REG_32BIT); 538 if (ret) 539 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 540 541 /* 542 * 19. Set COMPHY input port PIN_TX_IDLE=0 543 */ 544 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 545 0x0, PIN_TX_IDLE_BIT); 546 547 /* 548 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 549 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 550 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 551 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 552 * refer to RX initialization part for details. 553 */ 554 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 555 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 556 557 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 558 COMPHY_PHY_STATUS_OFFSET(comphy_index), 559 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 560 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 561 COMPHY_PLL_TIMEOUT, REG_32BIT); 562 if (ret) 563 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 564 565 566 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 567 COMPHY_PHY_STATUS_OFFSET(comphy_index), 568 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 569 COMPHY_PLL_TIMEOUT, REG_32BIT); 570 if (ret) 571 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 572 573 debug_exit(); 574 575 return ret; 576 } 577 578 static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) 579 { 580 int ret = 0; 581 uint32_t mask, data, offset; 582 583 debug_enter(); 584 585 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; 586 mask = data; 587 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 588 reg_set(offset, data, mask); 589 590 debug_exit(); 591 592 return ret; 593 } 594 595 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 596 uint32_t comphy_mode) 597 { 598 int ret = 0; 599 uintptr_t reg_base = 0; 600 uint32_t mask, data, addr, cfg, ref_clk; 601 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 602 uint16_t mask); 603 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 604 605 debug_enter(); 606 607 /* Set phy seclector */ 608 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 609 610 /* Set usb3 reg access func, Lane2 is indirect access */ 611 if (comphy_index == COMPHY_LANE2) { 612 usb3_reg_set = &comphy_usb3_set_indirect; 613 reg_base = COMPHY_INDIRECT_REG; 614 } else { 615 /* Get the direct access register resource and map */ 616 usb3_reg_set = &comphy_usb3_set_direct; 617 reg_base = USB3_GBE1_PHY; 618 } 619 620 /* 621 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 622 * register belong to UTMI module, so it is set in UTMI phy driver. 623 */ 624 625 /* 626 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 627 */ 628 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 629 CFG_TX_ALIGN_POS_MASK; 630 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, 631 mask); 632 633 /* 634 * 2. Set BIT0: enable transmitter in high impedance mode 635 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 636 * Set BIT6: Tx detect Rx at HiZ mode 637 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 638 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register 639 */ 640 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 641 TX_ELEC_IDLE_MODE_EN; 642 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 643 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask); 644 645 /* 646 * 3. Set Spread Spectrum Clock Enabled 647 */ 648 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, 649 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); 650 651 /* 652 * 4. Set Override Margining Controls From the MAC: 653 * Use margining signals from lane configuration 654 */ 655 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, 656 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK); 657 658 /* 659 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 660 * set Mode Clock Source = PCLK is generated from REFCLK 661 */ 662 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, 663 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | 664 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY)); 665 666 /* 667 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 668 */ 669 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, 670 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK); 671 672 /* 673 * 7. Unset G3 Spread Spectrum Clock Amplitude 674 * set G3 TX and RX Register Master Current Select 675 */ 676 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | 677 RSVD_PH03FH_6_0_MASK; 678 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, 679 G3_VREG_RXTX_MAS_ISET_60U, mask); 680 681 /* 682 * 8. Check crystal jumper setting and program the Power and PLL Control 683 * accordingly Change RX wait 684 */ 685 if (get_ref_clk() == 40) { 686 ref_clk = REF_CLOCK_SPEED_40M; 687 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 688 689 } else { 690 /* 25 MHz */ 691 ref_clk = USB3_REF_CLOCK_SPEED_25M; 692 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 693 } 694 695 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 696 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 697 REF_FREF_SEL_MASK; 698 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 699 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 700 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask); 701 702 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 703 CFG_PM_RXDLOZ_WAIT_MASK; 704 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 705 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask); 706 707 /* 708 * 9. Enable idle sync 709 */ 710 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; 711 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK); 712 713 /* 714 * 10. Enable the output of 500M clock 715 */ 716 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; 717 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK); 718 719 /* 720 * 11. Set 20-bit data width 721 */ 722 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, 723 REG_16_BIT_MASK); 724 725 /* 726 * 12. Override Speed_PLL value and use MAC PLL 727 */ 728 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 729 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 730 REG_16_BIT_MASK); 731 732 /* 733 * 13. Check the Polarity invert bit 734 */ 735 data = 0U; 736 if (invert & COMPHY_POLARITY_TXD_INVERT) { 737 data |= TXD_INVERT_BIT; 738 } 739 if (invert & COMPHY_POLARITY_RXD_INVERT) { 740 data |= RXD_INVERT_BIT; 741 } 742 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 743 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask); 744 745 /* 746 * 14. Set max speed generation to USB3.0 5Gbps 747 */ 748 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, 749 PHY_GEN_MAX_MASK); 750 751 /* 752 * 15. Set capacitor value for FFE gain peaking to 0xF 753 */ 754 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, 755 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK); 756 757 /* 758 * 16. Release SW reset 759 */ 760 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 761 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, 762 REG_16_BIT_MASK); 763 764 /* Wait for > 55 us to allow PCLK be enabled */ 765 udelay(PLL_SET_DELAY_US); 766 767 if (comphy_index == COMPHY_LANE2) { 768 data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; 769 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 770 data); 771 772 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; 773 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 774 COMPHY_PLL_TIMEOUT, REG_32BIT); 775 } else { 776 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, 777 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 778 COMPHY_PLL_TIMEOUT, REG_16BIT); 779 } 780 if (ret) 781 ERROR("Failed to lock USB3 PLL\n"); 782 783 debug_exit(); 784 785 return ret; 786 } 787 788 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 789 uint32_t comphy_mode) 790 { 791 int ret; 792 uint32_t ref_clk; 793 uint32_t mask, data; 794 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 795 796 debug_enter(); 797 798 /* 1. Enable max PLL. */ 799 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 800 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 801 802 /* 2. Select 20 bit SERDES interface. */ 803 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 804 CFG_SEL_20B, CFG_SEL_20B); 805 806 /* 3. Force to use reg setting for PCIe mode */ 807 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, 808 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 809 810 /* 4. Change RX wait */ 811 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 812 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 813 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 814 CFG_PM_RXDLOZ_WAIT_MASK)); 815 816 /* 5. Enable idle sync */ 817 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 818 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 819 820 /* 6. Enable the output of 100M/125M/500M clock */ 821 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, 822 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, 823 REG_16_BIT_MASK); 824 825 /* 826 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 827 * PCI-E driver 828 */ 829 830 /* 831 * 8. Check crystal jumper setting and program the Power and PLL 832 * Control accordingly 833 */ 834 835 if (get_ref_clk() == 40) 836 ref_clk = REF_CLOCK_SPEED_40M; 837 else 838 ref_clk = PCIE_REF_CLOCK_SPEED_25M; 839 840 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 841 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 842 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 843 REG_16_BIT_MASK); 844 845 /* 9. Override Speed_PLL value and use MAC PLL */ 846 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 847 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 848 849 /* 10. Check the Polarity invert bit */ 850 data = 0U; 851 if (invert & COMPHY_POLARITY_TXD_INVERT) { 852 data |= TXD_INVERT_BIT; 853 } 854 if (invert & COMPHY_POLARITY_RXD_INVERT) { 855 data |= RXD_INVERT_BIT; 856 } 857 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 858 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); 859 860 /* 11. Release SW reset */ 861 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 862 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, 863 SOFT_RESET | MODE_REFDIV); 864 865 /* Wait for > 55 us to allow PCLK be enabled */ 866 udelay(PLL_SET_DELAY_US); 867 868 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, 869 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 870 COMPHY_PLL_TIMEOUT, REG_16BIT); 871 if (ret) 872 ERROR("Failed to lock PCIE PLL\n"); 873 874 debug_exit(); 875 876 return ret; 877 } 878 879 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 880 { 881 int mode = COMPHY_GET_MODE(comphy_mode); 882 int ret = 0; 883 884 debug_enter(); 885 886 switch (mode) { 887 case(COMPHY_SATA_MODE): 888 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 889 comphy_mode); 890 break; 891 case(COMPHY_SGMII_MODE): 892 case(COMPHY_2500BASEX_MODE): 893 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 894 comphy_mode); 895 break; 896 case (COMPHY_USB3_MODE): 897 case (COMPHY_USB3H_MODE): 898 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 899 comphy_mode); 900 break; 901 case (COMPHY_PCIE_MODE): 902 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 903 comphy_mode); 904 break; 905 default: 906 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 907 ret = -EINVAL; 908 break; 909 } 910 911 debug_exit(); 912 913 return ret; 914 } 915 916 static int mvebu_a3700_comphy_usb3_power_off(void) 917 { 918 /* 919 * Currently the USB3 MAC will control the USB3 PHY to set it to low 920 * state, thus do not need to power off USB3 PHY again. 921 */ 922 debug_enter(); 923 debug_exit(); 924 925 return 0; 926 } 927 928 static int mvebu_a3700_comphy_sata_power_off(void) 929 { 930 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 931 uint32_t offset; 932 933 debug_enter(); 934 935 /* Set phy isolation mode */ 936 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 937 comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 938 PHY_ISOLATE_MODE); 939 940 /* Power off PLL, Tx, Rx */ 941 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 942 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, 943 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 944 945 debug_exit(); 946 947 return 0; 948 } 949 950 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 951 { 952 int mode = COMPHY_GET_MODE(comphy_mode); 953 int err = 0; 954 955 debug_enter(); 956 957 if (!mode) { 958 /* 959 * The user did not specify which mode should be powered off. 960 * In this case we can identify this by reading the phy selector 961 * register. 962 */ 963 mode = mvebu_a3700_comphy_get_mode(comphy_index); 964 } 965 966 switch (mode) { 967 case(COMPHY_SGMII_MODE): 968 case(COMPHY_2500BASEX_MODE): 969 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index); 970 break; 971 case (COMPHY_USB3_MODE): 972 case (COMPHY_USB3H_MODE): 973 err = mvebu_a3700_comphy_usb3_power_off(); 974 break; 975 case (COMPHY_SATA_MODE): 976 err = mvebu_a3700_comphy_sata_power_off(); 977 break; 978 979 default: 980 debug("comphy%d: power off is not implemented for mode %d\n", 981 comphy_index, mode); 982 break; 983 } 984 985 debug_exit(); 986 987 return err; 988 } 989 990 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 991 { 992 uint32_t data, addr; 993 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 994 int ret = 0; 995 996 debug_enter(); 997 998 /* Polling status */ 999 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 1000 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 1001 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 1002 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 1003 COMPHY_PLL_TIMEOUT, REG_32BIT); 1004 1005 if (data != 0) { 1006 ERROR("TX PLL is not locked\n"); 1007 ret = -ETIMEDOUT; 1008 } 1009 1010 debug_exit(); 1011 1012 return ret; 1013 } 1014 1015 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 1016 { 1017 int mode = COMPHY_GET_MODE(comphy_mode); 1018 int ret = 0; 1019 1020 debug_enter(); 1021 1022 switch (mode) { 1023 case(COMPHY_SATA_MODE): 1024 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 1025 break; 1026 1027 default: 1028 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 1029 comphy_index, mode); 1030 ret = -EINVAL; 1031 break; 1032 } 1033 1034 debug_exit(); 1035 1036 return ret; 1037 } 1038