1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 #include <plat_marvell.h> 18 19 #include "phy-comphy-3700.h" 20 #include "phy-comphy-common.h" 21 22 /* 23 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 24 * Linux is up to 0x178 so none will access it from Linux in runtime 25 * concurrently. 26 */ 27 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 28 29 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 30 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 31 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 32 33 struct sgmii_phy_init_data_fix { 34 uint16_t addr; 35 uint16_t value; 36 }; 37 38 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 39 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 40 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 41 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 42 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 43 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 44 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 45 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 46 {0x104, 0x0C10} 47 }; 48 49 /* 40M1G25 mode init data */ 50 static uint16_t sgmii_phy_init[512] = { 51 /* 0 1 2 3 4 5 6 7 */ 52 /*-----------------------------------------------------------*/ 53 /* 8 9 A B C D E F */ 54 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 55 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 56 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 57 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 58 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 59 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 60 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 61 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 62 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 63 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 64 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 65 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 66 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 67 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 68 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 69 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 70 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 71 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 72 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 73 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 74 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 75 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 77 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 78 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 79 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 80 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 81 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 82 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 83 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 84 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 85 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 86 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 88 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 101 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 118 }; 119 120 /* PHY selector configures with corresponding modes */ 121 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 122 uint32_t comphy_mode) 123 { 124 uint32_t reg; 125 int mode = COMPHY_GET_MODE(comphy_mode); 126 127 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 128 switch (mode) { 129 case (COMPHY_SATA_MODE): 130 /* SATA must be in Lane2 */ 131 if (comphy_index == COMPHY_LANE2) 132 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 133 else 134 goto error; 135 break; 136 137 case (COMPHY_SGMII_MODE): 138 case (COMPHY_2500BASEX_MODE): 139 if (comphy_index == COMPHY_LANE0) 140 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 141 else if (comphy_index == COMPHY_LANE1) 142 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 143 else 144 goto error; 145 break; 146 147 case (COMPHY_USB3H_MODE): 148 case (COMPHY_USB3D_MODE): 149 case (COMPHY_USB3_MODE): 150 if (comphy_index == COMPHY_LANE2) 151 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 152 else if (comphy_index == COMPHY_LANE0) 153 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 154 else 155 goto error; 156 break; 157 158 case (COMPHY_PCIE_MODE): 159 /* PCIE must be in Lane1 */ 160 if (comphy_index == COMPHY_LANE1) 161 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 162 else 163 goto error; 164 break; 165 166 default: 167 goto error; 168 } 169 170 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 171 return; 172 error: 173 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 174 } 175 176 /* 177 * This is something like the inverse of the previous function: for given 178 * lane it returns COMPHY_*_MODE. 179 * 180 * It is useful when powering the phy off. 181 * 182 * This function returns COMPHY_USB3_MODE even if the phy was configured 183 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization 184 * code does not differentiate between these modes.) 185 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with 186 * COMPHY_2500BASEX_MODE. (The sgmii phy initialization code does differentiate 187 * between these modes, but it is irrelevant when powering the phy off.) 188 */ 189 static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index) 190 { 191 uint32_t reg; 192 193 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 194 switch (comphy_index) { 195 case COMPHY_LANE0: 196 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0) 197 return COMPHY_USB3_MODE; 198 else 199 return COMPHY_SGMII_MODE; 200 case COMPHY_LANE1: 201 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0) 202 return COMPHY_PCIE_MODE; 203 else 204 return COMPHY_SGMII_MODE; 205 case COMPHY_LANE2: 206 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0) 207 return COMPHY_USB3_MODE; 208 else 209 return COMPHY_SATA_MODE; 210 } 211 212 return COMPHY_UNUSED; 213 } 214 215 /* It is only used for SATA and USB3 on comphy lane2. */ 216 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 217 uint16_t mask, bool is_sata) 218 { 219 /* 220 * When Lane 2 PHY is for USB3, access the PHY registers 221 * through indirect Address and Data registers: 222 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 223 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 224 * within the SATA Host Controller registers, Lane 2 base register 225 * offset is 0x200 226 */ 227 if (is_sata) { 228 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 229 } else { 230 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 231 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 232 } 233 234 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 235 } 236 237 /* It is only used for SATA on comphy lane2. */ 238 static void comphy_sata_set_indirect(uintptr_t addr, uint32_t reg_offset, 239 uint16_t data, uint16_t mask) 240 { 241 comphy_set_indirect(addr, reg_offset, data, mask, true); 242 } 243 244 /* It is only used for USB3 indirect access on comphy lane2. */ 245 static void comphy_usb3_set_indirect(uintptr_t addr, uint32_t reg_offset, 246 uint16_t data, uint16_t mask) 247 { 248 comphy_set_indirect(addr, reg_offset, data, mask, false); 249 } 250 251 /* It is only used for USB3 direct access not on comphy lane2. */ 252 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 253 uint16_t data, uint16_t mask) 254 { 255 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 256 } 257 258 static void comphy_sgmii_phy_init(uintptr_t sd_ip_addr, bool is_1gbps) 259 { 260 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 261 int addr, fix_idx; 262 uint16_t val; 263 264 fix_idx = 0; 265 for (addr = 0; addr < 512; addr++) { 266 /* 267 * All PHY register values are defined in full for 3.125Gbps 268 * SERDES speed. The values required for 1.25 Gbps are almost 269 * the same and only few registers should be "fixed" in 270 * comparison to 3.125 Gbps values. These register values are 271 * stored in "sgmii_phy_init_fix" array. 272 */ 273 if (!is_1gbps && sgmii_phy_init_fix[fix_idx].addr == addr) { 274 /* Use new value */ 275 val = sgmii_phy_init_fix[fix_idx].value; 276 if (fix_idx < fix_arr_sz) 277 fix_idx++; 278 } else { 279 val = sgmii_phy_init[addr]; 280 } 281 282 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 283 } 284 } 285 286 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 287 uint32_t comphy_mode) 288 { 289 int ret = 0; 290 uint32_t offset, data = 0, ref_clk; 291 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 292 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 293 294 debug_enter(); 295 296 /* Configure phy selector for SATA */ 297 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 298 299 /* Clear phy isolation mode to make it work in normal mode */ 300 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 301 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE); 302 303 /* 0. Check the Polarity invert bits */ 304 if (invert & COMPHY_POLARITY_TXD_INVERT) 305 data |= TXD_INVERT_BIT; 306 if (invert & COMPHY_POLARITY_RXD_INVERT) 307 data |= RXD_INVERT_BIT; 308 309 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 310 comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 311 RXD_INVERT_BIT); 312 313 /* 1. Select 40-bit data width width */ 314 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; 315 comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 316 SEL_DATA_WIDTH_MASK); 317 318 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 319 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 320 if (get_ref_clk() == 40) 321 ref_clk = REF_CLOCK_SPEED_40M; 322 else 323 ref_clk = REF_CLOCK_SPEED_25M; 324 325 comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 326 REF_FREF_SEL_MASK | PHY_MODE_MASK); 327 328 /* 3. Use maximum PLL rate (no power save) */ 329 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 330 comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 331 USE_MAX_PLL_RATE_BIT); 332 333 /* 4. Reset reserved bit */ 334 comphy_sata_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 335 PHYCTRL_FRM_PIN_BIT); 336 337 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 338 /* XXX: in U-Boot below sequence was executed in this place, in Linux 339 * not. Now it is done only in U-Boot before this comphy 340 * initialization - tests shows that it works ok, but in case of any 341 * future problem it is left for reference. 342 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 343 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 344 */ 345 346 /* Wait for > 55 us to allow PLL be enabled */ 347 udelay(PLL_SET_DELAY_US); 348 349 /* Polling status */ 350 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 351 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 352 353 ret = polling_with_timeout(comphy_indir_regs + 354 COMPHY_LANE2_INDIR_DATA_OFFSET, 355 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 356 COMPHY_PLL_TIMEOUT, REG_32BIT); 357 358 debug_exit(); 359 360 return ret; 361 } 362 363 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 364 uint32_t comphy_mode) 365 { 366 int ret = 0; 367 uint32_t mask, data; 368 uintptr_t offset; 369 uintptr_t sd_ip_addr; 370 int mode = COMPHY_GET_MODE(comphy_mode); 371 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 372 373 debug_enter(); 374 375 /* Set selector */ 376 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 377 378 /* Serdes IP Base address 379 * COMPHY Lane0 -- USB3/GBE1 380 * COMPHY Lane1 -- PCIe/GBE0 381 */ 382 if (comphy_index == COMPHY_LANE0) { 383 /* Get usb3 and gbe */ 384 sd_ip_addr = USB3_GBE1_PHY; 385 } else 386 sd_ip_addr = COMPHY_SD_ADDR; 387 388 /* 389 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 390 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 391 * PHY TXP/TXN output to idle state during PHY initialization 392 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 393 */ 394 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 395 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 396 PIN_PU_TX_BIT; 397 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 398 reg_set(offset, data, mask); 399 400 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 401 data = 0; 402 mask = PIN_RESET_COMPHY_BIT; 403 reg_set(offset, data, mask); 404 405 /* 406 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 407 * bit rate 408 */ 409 if (mode == COMPHY_SGMII_MODE) { 410 /* SGMII 1G, SerDes speed 1.25G */ 411 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 412 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 413 } else if (mode == COMPHY_2500BASEX_MODE) { 414 /* 2500Base-X, SerDes speed 3.125G */ 415 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; 416 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; 417 } else { 418 /* Other rates are not supported */ 419 ERROR("unsupported SGMII speed on comphy lane%d\n", 420 comphy_index); 421 return -EINVAL; 422 } 423 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 424 reg_set(offset, data, mask); 425 426 /* 427 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 428 * start SW programming. 429 */ 430 mdelay(10); 431 432 /* 7. Program COMPHY register PHY_MODE */ 433 data = PHY_MODE_SGMII; 434 mask = PHY_MODE_MASK; 435 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 436 437 /* 438 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 439 * source 440 */ 441 data = 0; 442 mask = PHY_REF_CLK_SEL; 443 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); 444 445 /* 446 * 9. Set correct reference clock frequency in COMPHY register 447 * REF_FREF_SEL. 448 */ 449 if (get_ref_clk() == 40) 450 data = REF_CLOCK_SPEED_50M; 451 else 452 data = REF_CLOCK_SPEED_25M; 453 454 mask = REF_FREF_SEL_MASK; 455 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 456 457 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 458 * This step is mentioned in the flow received from verification team. 459 * However the PHY_GEN_MAX value is only meaningful for other interfaces 460 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 461 * speed 2.5/5 Gbps 462 */ 463 464 /* 465 * 11. Program COMPHY register SEL_BITS to set correct parallel data 466 * bus width 467 */ 468 data = DATA_WIDTH_10BIT; 469 mask = SEL_DATA_WIDTH_MASK; 470 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); 471 472 /* 473 * 12. As long as DFE function needs to be enabled in any mode, 474 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 475 * for real chip during COMPHY power on. 476 * The step 14 exists (and empty) in the original initialization flow 477 * obtained from the verification team. According to the functional 478 * specification DFE_UPDATE_EN already has the default value 0x3F 479 */ 480 481 /* 482 * 13. Program COMPHY GEN registers. 483 * These registers should be programmed based on the lab testing result 484 * to achieve optimal performance. Please contact the CEA group to get 485 * the related GEN table during real chip bring-up. We only required to 486 * run though the entire registers programming flow defined by 487 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 488 * 25 MHz the default values stored in PHY registers are OK. 489 */ 490 debug("Running C-DPI phy init %s mode\n", 491 mode == COMPHY_2500BASEX_MODE ? "2G5" : "1G"); 492 if (get_ref_clk() == 40) 493 comphy_sgmii_phy_init(sd_ip_addr, mode != COMPHY_2500BASEX_MODE); 494 495 /* 496 * 14. [Simulation Only] should not be used for real chip. 497 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 498 * (R02h[9]) to 1 to shorten COMPHY simulation time. 499 */ 500 501 /* 502 * 15. [Simulation Only: should not be used for real chip] 503 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 504 * simulation time. 505 */ 506 507 /* 508 * 16. Check the PHY Polarity invert bit 509 */ 510 data = 0x0; 511 if (invert & COMPHY_POLARITY_TXD_INVERT) 512 data |= TXD_INVERT_BIT; 513 if (invert & COMPHY_POLARITY_RXD_INVERT) 514 data |= RXD_INVERT_BIT; 515 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 516 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask); 517 518 /* 519 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 520 * start PHY power up sequence. All the PHY register programming should 521 * be done before PIN_PU_PLL=1. There should be no register programming 522 * for normal PHY operation from this point. 523 */ 524 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 525 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 526 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 527 528 /* 529 * 18. Wait for PHY power up sequence to finish by checking output ports 530 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 531 */ 532 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 533 COMPHY_PHY_STATUS_OFFSET(comphy_index), 534 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 535 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 536 COMPHY_PLL_TIMEOUT, REG_32BIT); 537 if (ret) 538 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 539 540 /* 541 * 19. Set COMPHY input port PIN_TX_IDLE=0 542 */ 543 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 544 0x0, PIN_TX_IDLE_BIT); 545 546 /* 547 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 548 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 549 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 550 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 551 * refer to RX initialization part for details. 552 */ 553 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 554 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 555 556 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 557 COMPHY_PHY_STATUS_OFFSET(comphy_index), 558 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 559 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 560 COMPHY_PLL_TIMEOUT, REG_32BIT); 561 if (ret) 562 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 563 564 565 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 566 COMPHY_PHY_STATUS_OFFSET(comphy_index), 567 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 568 COMPHY_PLL_TIMEOUT, REG_32BIT); 569 if (ret) 570 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 571 572 debug_exit(); 573 574 return ret; 575 } 576 577 static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) 578 { 579 int ret = 0; 580 uintptr_t offset; 581 uint32_t mask, data; 582 583 debug_enter(); 584 585 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; 586 mask = data; 587 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 588 reg_set(offset, data, mask); 589 590 debug_exit(); 591 592 return ret; 593 } 594 595 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 596 uint32_t comphy_mode) 597 { 598 int ret = 0; 599 uintptr_t reg_base = 0; 600 uintptr_t addr; 601 uint32_t mask, data, cfg, ref_clk; 602 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 603 uint16_t mask); 604 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 605 606 debug_enter(); 607 608 /* Set phy seclector */ 609 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 610 611 /* Set usb3 reg access func, Lane2 is indirect access */ 612 if (comphy_index == COMPHY_LANE2) { 613 usb3_reg_set = &comphy_usb3_set_indirect; 614 reg_base = COMPHY_INDIRECT_REG; 615 } else { 616 /* Get the direct access register resource and map */ 617 usb3_reg_set = &comphy_usb3_set_direct; 618 reg_base = USB3_GBE1_PHY; 619 } 620 621 /* 622 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 623 * register belong to UTMI module, so it is set in UTMI phy driver. 624 */ 625 626 /* 627 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 628 */ 629 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 630 CFG_TX_ALIGN_POS_MASK; 631 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, 632 mask); 633 634 /* 635 * 2. Set BIT0: enable transmitter in high impedance mode 636 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 637 * Set BIT6: Tx detect Rx at HiZ mode 638 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 639 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register 640 */ 641 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 642 TX_ELEC_IDLE_MODE_EN; 643 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 644 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask); 645 646 /* 647 * 3. Set Spread Spectrum Clock Enabled 648 */ 649 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, 650 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); 651 652 /* 653 * 4. Set Override Margining Controls From the MAC: 654 * Use margining signals from lane configuration 655 */ 656 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, 657 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK); 658 659 /* 660 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 661 * set Mode Clock Source = PCLK is generated from REFCLK 662 */ 663 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, 664 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | 665 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY)); 666 667 /* 668 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 669 */ 670 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, 671 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK); 672 673 /* 674 * 7. Unset G3 Spread Spectrum Clock Amplitude 675 * set G3 TX and RX Register Master Current Select 676 */ 677 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | 678 RSVD_PH03FH_6_0_MASK; 679 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, 680 G3_VREG_RXTX_MAS_ISET_60U, mask); 681 682 /* 683 * 8. Check crystal jumper setting and program the Power and PLL Control 684 * accordingly Change RX wait 685 */ 686 if (get_ref_clk() == 40) { 687 ref_clk = REF_CLOCK_SPEED_40M; 688 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 689 690 } else { 691 /* 25 MHz */ 692 ref_clk = USB3_REF_CLOCK_SPEED_25M; 693 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 694 } 695 696 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 697 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 698 REF_FREF_SEL_MASK; 699 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 700 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 701 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask); 702 703 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 704 CFG_PM_RXDLOZ_WAIT_MASK; 705 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 706 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask); 707 708 /* 709 * 9. Enable idle sync 710 */ 711 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; 712 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK); 713 714 /* 715 * 10. Enable the output of 500M clock 716 */ 717 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; 718 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK); 719 720 /* 721 * 11. Set 20-bit data width 722 */ 723 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, 724 REG_16_BIT_MASK); 725 726 /* 727 * 12. Override Speed_PLL value and use MAC PLL 728 */ 729 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 730 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 731 REG_16_BIT_MASK); 732 733 /* 734 * 13. Check the Polarity invert bit 735 */ 736 data = 0U; 737 if (invert & COMPHY_POLARITY_TXD_INVERT) { 738 data |= TXD_INVERT_BIT; 739 } 740 if (invert & COMPHY_POLARITY_RXD_INVERT) { 741 data |= RXD_INVERT_BIT; 742 } 743 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 744 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask); 745 746 /* 747 * 14. Set max speed generation to USB3.0 5Gbps 748 */ 749 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, 750 PHY_GEN_MAX_MASK); 751 752 /* 753 * 15. Set capacitor value for FFE gain peaking to 0xF 754 */ 755 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, 756 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK); 757 758 /* 759 * 16. Release SW reset 760 */ 761 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 762 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, 763 REG_16_BIT_MASK); 764 765 /* Wait for > 55 us to allow PCLK be enabled */ 766 udelay(PLL_SET_DELAY_US); 767 768 if (comphy_index == COMPHY_LANE2) { 769 data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; 770 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 771 data); 772 773 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; 774 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 775 COMPHY_PLL_TIMEOUT, REG_32BIT); 776 } else { 777 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, 778 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 779 COMPHY_PLL_TIMEOUT, REG_16BIT); 780 } 781 if (ret) 782 ERROR("Failed to lock USB3 PLL\n"); 783 784 debug_exit(); 785 786 return ret; 787 } 788 789 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 790 uint32_t comphy_mode) 791 { 792 int ret; 793 uint32_t ref_clk; 794 uint32_t mask, data; 795 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 796 797 debug_enter(); 798 799 /* 1. Enable max PLL. */ 800 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 801 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 802 803 /* 2. Select 20 bit SERDES interface. */ 804 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 805 CFG_SEL_20B, CFG_SEL_20B); 806 807 /* 3. Force to use reg setting for PCIe mode */ 808 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, 809 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 810 811 /* 4. Change RX wait */ 812 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 813 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 814 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 815 CFG_PM_RXDLOZ_WAIT_MASK)); 816 817 /* 5. Enable idle sync */ 818 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 819 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 820 821 /* 6. Enable the output of 100M/125M/500M clock */ 822 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, 823 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, 824 REG_16_BIT_MASK); 825 826 /* 827 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 828 * PCI-E driver 829 */ 830 831 /* 832 * 8. Check crystal jumper setting and program the Power and PLL 833 * Control accordingly 834 */ 835 836 if (get_ref_clk() == 40) 837 ref_clk = REF_CLOCK_SPEED_40M; 838 else 839 ref_clk = PCIE_REF_CLOCK_SPEED_25M; 840 841 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 842 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 843 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 844 REG_16_BIT_MASK); 845 846 /* 9. Override Speed_PLL value and use MAC PLL */ 847 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 848 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 849 850 /* 10. Check the Polarity invert bit */ 851 data = 0U; 852 if (invert & COMPHY_POLARITY_TXD_INVERT) { 853 data |= TXD_INVERT_BIT; 854 } 855 if (invert & COMPHY_POLARITY_RXD_INVERT) { 856 data |= RXD_INVERT_BIT; 857 } 858 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 859 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); 860 861 /* 11. Release SW reset */ 862 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 863 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, 864 SOFT_RESET | MODE_REFDIV); 865 866 /* Wait for > 55 us to allow PCLK be enabled */ 867 udelay(PLL_SET_DELAY_US); 868 869 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, 870 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 871 COMPHY_PLL_TIMEOUT, REG_16BIT); 872 if (ret) 873 ERROR("Failed to lock PCIE PLL\n"); 874 875 debug_exit(); 876 877 return ret; 878 } 879 880 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 881 { 882 int mode = COMPHY_GET_MODE(comphy_mode); 883 int ret = 0; 884 885 debug_enter(); 886 887 switch (mode) { 888 case(COMPHY_SATA_MODE): 889 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 890 comphy_mode); 891 break; 892 case(COMPHY_SGMII_MODE): 893 case(COMPHY_2500BASEX_MODE): 894 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 895 comphy_mode); 896 break; 897 case (COMPHY_USB3_MODE): 898 case (COMPHY_USB3H_MODE): 899 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 900 comphy_mode); 901 break; 902 case (COMPHY_PCIE_MODE): 903 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 904 comphy_mode); 905 break; 906 default: 907 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 908 ret = -EINVAL; 909 break; 910 } 911 912 debug_exit(); 913 914 return ret; 915 } 916 917 static int mvebu_a3700_comphy_usb3_power_off(void) 918 { 919 /* 920 * Currently the USB3 MAC will control the USB3 PHY to set it to low 921 * state, thus do not need to power off USB3 PHY again. 922 */ 923 debug_enter(); 924 debug_exit(); 925 926 return 0; 927 } 928 929 static int mvebu_a3700_comphy_sata_power_off(void) 930 { 931 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 932 uint32_t offset; 933 934 debug_enter(); 935 936 /* Set phy isolation mode */ 937 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 938 comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 939 PHY_ISOLATE_MODE); 940 941 /* Power off PLL, Tx, Rx */ 942 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 943 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, 944 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 945 946 debug_exit(); 947 948 return 0; 949 } 950 951 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 952 { 953 int mode = COMPHY_GET_MODE(comphy_mode); 954 int err = 0; 955 956 debug_enter(); 957 958 if (!mode) { 959 /* 960 * The user did not specify which mode should be powered off. 961 * In this case we can identify this by reading the phy selector 962 * register. 963 */ 964 mode = mvebu_a3700_comphy_get_mode(comphy_index); 965 } 966 967 switch (mode) { 968 case(COMPHY_SGMII_MODE): 969 case(COMPHY_2500BASEX_MODE): 970 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index); 971 break; 972 case (COMPHY_USB3_MODE): 973 case (COMPHY_USB3H_MODE): 974 err = mvebu_a3700_comphy_usb3_power_off(); 975 break; 976 case (COMPHY_SATA_MODE): 977 err = mvebu_a3700_comphy_sata_power_off(); 978 break; 979 980 default: 981 debug("comphy%d: power off is not implemented for mode %d\n", 982 comphy_index, mode); 983 break; 984 } 985 986 debug_exit(); 987 988 return err; 989 } 990 991 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 992 { 993 uint32_t data, addr; 994 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 995 int ret = 0; 996 997 debug_enter(); 998 999 /* Polling status */ 1000 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 1001 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 1002 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 1003 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 1004 COMPHY_PLL_TIMEOUT, REG_32BIT); 1005 1006 if (data != 0) { 1007 ERROR("TX PLL is not locked\n"); 1008 ret = -ETIMEDOUT; 1009 } 1010 1011 debug_exit(); 1012 1013 return ret; 1014 } 1015 1016 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 1017 { 1018 int mode = COMPHY_GET_MODE(comphy_mode); 1019 int ret = 0; 1020 1021 debug_enter(); 1022 1023 switch (mode) { 1024 case(COMPHY_SATA_MODE): 1025 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 1026 break; 1027 1028 default: 1029 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 1030 comphy_index, mode); 1031 ret = -EINVAL; 1032 break; 1033 } 1034 1035 debug_exit(); 1036 1037 return ret; 1038 } 1039