1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 #include <plat_marvell.h> 18 19 #include "phy-comphy-3700.h" 20 #include "phy-comphy-common.h" 21 22 /* 23 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 24 * Linux is up to 0x178 so none will access it from Linux in runtime 25 * concurrently. 26 */ 27 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 28 29 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 30 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 31 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 32 33 struct sgmii_phy_init_data_fix { 34 uint16_t addr; 35 uint16_t value; 36 }; 37 38 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 39 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 40 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 41 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 42 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 43 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 44 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 45 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 46 {0x104, 0x0C10} 47 }; 48 49 /* 40M1G25 mode init data */ 50 static uint16_t sgmii_phy_init[512] = { 51 /* 0 1 2 3 4 5 6 7 */ 52 /*-----------------------------------------------------------*/ 53 /* 8 9 A B C D E F */ 54 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 55 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 56 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 57 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 58 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 59 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 60 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 61 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 62 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 63 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 64 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 65 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 66 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 67 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 68 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 69 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 70 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 71 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 72 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 73 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 74 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 75 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 77 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 78 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 79 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 80 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 81 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 82 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 83 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 84 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 85 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 86 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 88 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 101 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 118 }; 119 120 /* PHY selector configures with corresponding modes */ 121 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 122 uint32_t comphy_mode) 123 { 124 uint32_t reg; 125 int mode = COMPHY_GET_MODE(comphy_mode); 126 127 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 128 switch (mode) { 129 case (COMPHY_SATA_MODE): 130 /* SATA must be in Lane2 */ 131 if (comphy_index == COMPHY_LANE2) 132 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 133 else 134 goto error; 135 break; 136 137 case (COMPHY_SGMII_MODE): 138 case (COMPHY_2500BASEX_MODE): 139 if (comphy_index == COMPHY_LANE0) 140 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 141 else if (comphy_index == COMPHY_LANE1) 142 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 143 else 144 goto error; 145 break; 146 147 case (COMPHY_USB3H_MODE): 148 case (COMPHY_USB3D_MODE): 149 case (COMPHY_USB3_MODE): 150 if (comphy_index == COMPHY_LANE2) 151 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 152 else if (comphy_index == COMPHY_LANE0) 153 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 154 else 155 goto error; 156 break; 157 158 case (COMPHY_PCIE_MODE): 159 /* PCIE must be in Lane1 */ 160 if (comphy_index == COMPHY_LANE1) 161 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 162 else 163 goto error; 164 break; 165 166 default: 167 goto error; 168 } 169 170 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 171 return; 172 error: 173 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 174 } 175 176 /* 177 * This is something like the inverse of the previous function: for given 178 * lane it returns COMPHY_*_MODE. 179 * 180 * It is useful when powering the phy off. 181 * 182 * This function returns COMPHY_USB3_MODE even if the phy was configured 183 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization 184 * code does not differentiate between these modes.) 185 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with 186 * COMPHY_2500BASEX_MODE. (The sgmii phy initialization code does differentiate 187 * between these modes, but it is irrelevant when powering the phy off.) 188 */ 189 static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index) 190 { 191 uint32_t reg; 192 193 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 194 switch (comphy_index) { 195 case COMPHY_LANE0: 196 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0) 197 return COMPHY_USB3_MODE; 198 else 199 return COMPHY_SGMII_MODE; 200 case COMPHY_LANE1: 201 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0) 202 return COMPHY_PCIE_MODE; 203 else 204 return COMPHY_SGMII_MODE; 205 case COMPHY_LANE2: 206 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0) 207 return COMPHY_USB3_MODE; 208 else 209 return COMPHY_SATA_MODE; 210 } 211 212 return COMPHY_UNUSED; 213 } 214 215 /* It is only used for SATA and USB3 on comphy lane2. */ 216 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 217 uint16_t mask, bool is_sata) 218 { 219 /* 220 * When Lane 2 PHY is for USB3, access the PHY registers 221 * through indirect Address and Data registers: 222 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 223 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 224 * within the SATA Host Controller registers, Lane 2 base register 225 * offset is 0x200 226 */ 227 if (is_sata) { 228 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 229 } else { 230 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 231 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 232 } 233 234 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 235 } 236 237 /* It is only used for SATA on comphy lane2. */ 238 static void comphy_sata_set_indirect(uintptr_t addr, uint32_t reg_offset, 239 uint16_t data, uint16_t mask) 240 { 241 comphy_set_indirect(addr, reg_offset, data, mask, true); 242 } 243 244 /* It is only used for USB3 indirect access on comphy lane2. */ 245 static void comphy_usb3_set_indirect(uintptr_t addr, uint32_t reg_offset, 246 uint16_t data, uint16_t mask) 247 { 248 comphy_set_indirect(addr, reg_offset, data, mask, false); 249 } 250 251 /* It is only used for USB3 direct access not on comphy lane2. */ 252 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 253 uint16_t data, uint16_t mask) 254 { 255 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 256 } 257 258 static void comphy_sgmii_phy_init(uintptr_t sd_ip_addr, bool is_1gbps) 259 { 260 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 261 int addr, fix_idx; 262 uint16_t val; 263 264 fix_idx = 0; 265 for (addr = 0; addr < 512; addr++) { 266 /* 267 * All PHY register values are defined in full for 3.125Gbps 268 * SERDES speed. The values required for 1.25 Gbps are almost 269 * the same and only few registers should be "fixed" in 270 * comparison to 3.125 Gbps values. These register values are 271 * stored in "sgmii_phy_init_fix" array. 272 */ 273 if (!is_1gbps && sgmii_phy_init_fix[fix_idx].addr == addr) { 274 /* Use new value */ 275 val = sgmii_phy_init_fix[fix_idx].value; 276 if (fix_idx < fix_arr_sz) 277 fix_idx++; 278 } else { 279 val = sgmii_phy_init[addr]; 280 } 281 282 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 283 } 284 } 285 286 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 287 uint32_t comphy_mode) 288 { 289 int ret = 0; 290 uint32_t offset, data = 0, ref_clk; 291 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 292 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 293 294 debug_enter(); 295 296 /* Configure phy selector for SATA */ 297 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 298 299 /* Clear phy isolation mode to make it work in normal mode */ 300 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 301 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE); 302 303 /* 0. Check the Polarity invert bits */ 304 if (invert & COMPHY_POLARITY_TXD_INVERT) 305 data |= TXD_INVERT_BIT; 306 if (invert & COMPHY_POLARITY_RXD_INVERT) 307 data |= RXD_INVERT_BIT; 308 309 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 310 comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 311 RXD_INVERT_BIT); 312 313 /* 1. Select 40-bit data width width */ 314 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; 315 comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 316 SEL_DATA_WIDTH_MASK); 317 318 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 319 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 320 if (get_ref_clk() == 40) 321 ref_clk = REF_CLOCK_SPEED_40M; 322 else 323 ref_clk = REF_CLOCK_SPEED_25M; 324 325 comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 326 REF_FREF_SEL_MASK | PHY_MODE_MASK); 327 328 /* 3. Use maximum PLL rate (no power save) */ 329 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 330 comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 331 USE_MAX_PLL_RATE_BIT); 332 333 /* 4. Reset reserved bit */ 334 comphy_sata_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 335 PHYCTRL_FRM_PIN_BIT); 336 337 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 338 /* XXX: in U-Boot below sequence was executed in this place, in Linux 339 * not. Now it is done only in U-Boot before this comphy 340 * initialization - tests shows that it works ok, but in case of any 341 * future problem it is left for reference. 342 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 343 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 344 */ 345 346 /* Wait for > 55 us to allow PLL be enabled */ 347 udelay(PLL_SET_DELAY_US); 348 349 /* Polling status */ 350 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 351 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 352 353 ret = polling_with_timeout(comphy_indir_regs + 354 COMPHY_LANE2_INDIR_DATA_OFFSET, 355 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 356 COMPHY_PLL_TIMEOUT, REG_32BIT); 357 358 debug_exit(); 359 360 return ret; 361 } 362 363 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 364 uint32_t comphy_mode) 365 { 366 int ret = 0; 367 uint32_t mask, data, offset; 368 uintptr_t sd_ip_addr; 369 int mode = COMPHY_GET_MODE(comphy_mode); 370 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 371 372 debug_enter(); 373 374 /* Set selector */ 375 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 376 377 /* Serdes IP Base address 378 * COMPHY Lane0 -- USB3/GBE1 379 * COMPHY Lane1 -- PCIe/GBE0 380 */ 381 if (comphy_index == COMPHY_LANE0) { 382 /* Get usb3 and gbe */ 383 sd_ip_addr = USB3_GBE1_PHY; 384 } else 385 sd_ip_addr = COMPHY_SD_ADDR; 386 387 /* 388 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 389 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 390 * PHY TXP/TXN output to idle state during PHY initialization 391 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 392 */ 393 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 394 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 395 PIN_PU_TX_BIT; 396 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 397 reg_set(offset, data, mask); 398 399 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 400 data = 0; 401 mask = PIN_RESET_COMPHY_BIT; 402 reg_set(offset, data, mask); 403 404 /* 405 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 406 * bit rate 407 */ 408 if (mode == COMPHY_SGMII_MODE) { 409 /* SGMII 1G, SerDes speed 1.25G */ 410 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 411 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 412 } else if (mode == COMPHY_2500BASEX_MODE) { 413 /* 2500Base-X, SerDes speed 3.125G */ 414 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; 415 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; 416 } else { 417 /* Other rates are not supported */ 418 ERROR("unsupported SGMII speed on comphy lane%d\n", 419 comphy_index); 420 return -EINVAL; 421 } 422 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 423 reg_set(offset, data, mask); 424 425 /* 426 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 427 * start SW programming. 428 */ 429 mdelay(10); 430 431 /* 7. Program COMPHY register PHY_MODE */ 432 data = PHY_MODE_SGMII; 433 mask = PHY_MODE_MASK; 434 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 435 436 /* 437 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 438 * source 439 */ 440 data = 0; 441 mask = PHY_REF_CLK_SEL; 442 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); 443 444 /* 445 * 9. Set correct reference clock frequency in COMPHY register 446 * REF_FREF_SEL. 447 */ 448 if (get_ref_clk() == 40) 449 data = REF_CLOCK_SPEED_50M; 450 else 451 data = REF_CLOCK_SPEED_25M; 452 453 mask = REF_FREF_SEL_MASK; 454 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 455 456 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 457 * This step is mentioned in the flow received from verification team. 458 * However the PHY_GEN_MAX value is only meaningful for other interfaces 459 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 460 * speed 2.5/5 Gbps 461 */ 462 463 /* 464 * 11. Program COMPHY register SEL_BITS to set correct parallel data 465 * bus width 466 */ 467 data = DATA_WIDTH_10BIT; 468 mask = SEL_DATA_WIDTH_MASK; 469 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); 470 471 /* 472 * 12. As long as DFE function needs to be enabled in any mode, 473 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 474 * for real chip during COMPHY power on. 475 * The step 14 exists (and empty) in the original initialization flow 476 * obtained from the verification team. According to the functional 477 * specification DFE_UPDATE_EN already has the default value 0x3F 478 */ 479 480 /* 481 * 13. Program COMPHY GEN registers. 482 * These registers should be programmed based on the lab testing result 483 * to achieve optimal performance. Please contact the CEA group to get 484 * the related GEN table during real chip bring-up. We only required to 485 * run though the entire registers programming flow defined by 486 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 487 * 25 MHz the default values stored in PHY registers are OK. 488 */ 489 debug("Running C-DPI phy init %s mode\n", 490 mode == COMPHY_2500BASEX_MODE ? "2G5" : "1G"); 491 if (get_ref_clk() == 40) 492 comphy_sgmii_phy_init(sd_ip_addr, mode != COMPHY_2500BASEX_MODE); 493 494 /* 495 * 14. [Simulation Only] should not be used for real chip. 496 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 497 * (R02h[9]) to 1 to shorten COMPHY simulation time. 498 */ 499 500 /* 501 * 15. [Simulation Only: should not be used for real chip] 502 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 503 * simulation time. 504 */ 505 506 /* 507 * 16. Check the PHY Polarity invert bit 508 */ 509 data = 0x0; 510 if (invert & COMPHY_POLARITY_TXD_INVERT) 511 data |= TXD_INVERT_BIT; 512 if (invert & COMPHY_POLARITY_RXD_INVERT) 513 data |= RXD_INVERT_BIT; 514 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 515 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask); 516 517 /* 518 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 519 * start PHY power up sequence. All the PHY register programming should 520 * be done before PIN_PU_PLL=1. There should be no register programming 521 * for normal PHY operation from this point. 522 */ 523 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 524 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 525 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 526 527 /* 528 * 18. Wait for PHY power up sequence to finish by checking output ports 529 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 530 */ 531 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 532 COMPHY_PHY_STATUS_OFFSET(comphy_index), 533 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 534 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 535 COMPHY_PLL_TIMEOUT, REG_32BIT); 536 if (ret) 537 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 538 539 /* 540 * 19. Set COMPHY input port PIN_TX_IDLE=0 541 */ 542 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 543 0x0, PIN_TX_IDLE_BIT); 544 545 /* 546 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 547 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 548 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 549 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 550 * refer to RX initialization part for details. 551 */ 552 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 553 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 554 555 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 556 COMPHY_PHY_STATUS_OFFSET(comphy_index), 557 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 558 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 559 COMPHY_PLL_TIMEOUT, REG_32BIT); 560 if (ret) 561 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 562 563 564 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 565 COMPHY_PHY_STATUS_OFFSET(comphy_index), 566 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 567 COMPHY_PLL_TIMEOUT, REG_32BIT); 568 if (ret) 569 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 570 571 debug_exit(); 572 573 return ret; 574 } 575 576 static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) 577 { 578 int ret = 0; 579 uint32_t mask, data, offset; 580 581 debug_enter(); 582 583 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; 584 mask = data; 585 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 586 reg_set(offset, data, mask); 587 588 debug_exit(); 589 590 return ret; 591 } 592 593 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 594 uint32_t comphy_mode) 595 { 596 int ret = 0; 597 uintptr_t reg_base = 0; 598 uint32_t mask, data, addr, cfg, ref_clk; 599 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 600 uint16_t mask); 601 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 602 603 debug_enter(); 604 605 /* Set phy seclector */ 606 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 607 608 /* Set usb3 reg access func, Lane2 is indirect access */ 609 if (comphy_index == COMPHY_LANE2) { 610 usb3_reg_set = &comphy_usb3_set_indirect; 611 reg_base = COMPHY_INDIRECT_REG; 612 } else { 613 /* Get the direct access register resource and map */ 614 usb3_reg_set = &comphy_usb3_set_direct; 615 reg_base = USB3_GBE1_PHY; 616 } 617 618 /* 619 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 620 * register belong to UTMI module, so it is set in UTMI phy driver. 621 */ 622 623 /* 624 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 625 */ 626 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 627 CFG_TX_ALIGN_POS_MASK; 628 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, 629 mask); 630 631 /* 632 * 2. Set BIT0: enable transmitter in high impedance mode 633 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 634 * Set BIT6: Tx detect Rx at HiZ mode 635 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 636 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register 637 */ 638 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 639 TX_ELEC_IDLE_MODE_EN; 640 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 641 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask); 642 643 /* 644 * 3. Set Spread Spectrum Clock Enabled 645 */ 646 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, 647 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); 648 649 /* 650 * 4. Set Override Margining Controls From the MAC: 651 * Use margining signals from lane configuration 652 */ 653 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, 654 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK); 655 656 /* 657 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 658 * set Mode Clock Source = PCLK is generated from REFCLK 659 */ 660 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, 661 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | 662 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY)); 663 664 /* 665 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 666 */ 667 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, 668 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK); 669 670 /* 671 * 7. Unset G3 Spread Spectrum Clock Amplitude 672 * set G3 TX and RX Register Master Current Select 673 */ 674 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | 675 RSVD_PH03FH_6_0_MASK; 676 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, 677 G3_VREG_RXTX_MAS_ISET_60U, mask); 678 679 /* 680 * 8. Check crystal jumper setting and program the Power and PLL Control 681 * accordingly Change RX wait 682 */ 683 if (get_ref_clk() == 40) { 684 ref_clk = REF_CLOCK_SPEED_40M; 685 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 686 687 } else { 688 /* 25 MHz */ 689 ref_clk = USB3_REF_CLOCK_SPEED_25M; 690 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 691 } 692 693 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 694 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 695 REF_FREF_SEL_MASK; 696 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 697 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 698 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask); 699 700 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 701 CFG_PM_RXDLOZ_WAIT_MASK; 702 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 703 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask); 704 705 /* 706 * 9. Enable idle sync 707 */ 708 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; 709 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK); 710 711 /* 712 * 10. Enable the output of 500M clock 713 */ 714 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; 715 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK); 716 717 /* 718 * 11. Set 20-bit data width 719 */ 720 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, 721 REG_16_BIT_MASK); 722 723 /* 724 * 12. Override Speed_PLL value and use MAC PLL 725 */ 726 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 727 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 728 REG_16_BIT_MASK); 729 730 /* 731 * 13. Check the Polarity invert bit 732 */ 733 data = 0U; 734 if (invert & COMPHY_POLARITY_TXD_INVERT) { 735 data |= TXD_INVERT_BIT; 736 } 737 if (invert & COMPHY_POLARITY_RXD_INVERT) { 738 data |= RXD_INVERT_BIT; 739 } 740 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 741 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask); 742 743 /* 744 * 14. Set max speed generation to USB3.0 5Gbps 745 */ 746 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, 747 PHY_GEN_MAX_MASK); 748 749 /* 750 * 15. Set capacitor value for FFE gain peaking to 0xF 751 */ 752 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, 753 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK); 754 755 /* 756 * 16. Release SW reset 757 */ 758 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 759 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, 760 REG_16_BIT_MASK); 761 762 /* Wait for > 55 us to allow PCLK be enabled */ 763 udelay(PLL_SET_DELAY_US); 764 765 if (comphy_index == COMPHY_LANE2) { 766 data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; 767 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 768 data); 769 770 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; 771 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 772 COMPHY_PLL_TIMEOUT, REG_32BIT); 773 } else { 774 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, 775 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 776 COMPHY_PLL_TIMEOUT, REG_16BIT); 777 } 778 if (ret) 779 ERROR("Failed to lock USB3 PLL\n"); 780 781 debug_exit(); 782 783 return ret; 784 } 785 786 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 787 uint32_t comphy_mode) 788 { 789 int ret; 790 uint32_t ref_clk; 791 uint32_t mask, data; 792 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 793 794 debug_enter(); 795 796 /* 1. Enable max PLL. */ 797 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 798 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 799 800 /* 2. Select 20 bit SERDES interface. */ 801 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 802 CFG_SEL_20B, CFG_SEL_20B); 803 804 /* 3. Force to use reg setting for PCIe mode */ 805 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, 806 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 807 808 /* 4. Change RX wait */ 809 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 810 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 811 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 812 CFG_PM_RXDLOZ_WAIT_MASK)); 813 814 /* 5. Enable idle sync */ 815 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 816 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 817 818 /* 6. Enable the output of 100M/125M/500M clock */ 819 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, 820 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, 821 REG_16_BIT_MASK); 822 823 /* 824 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 825 * PCI-E driver 826 */ 827 828 /* 829 * 8. Check crystal jumper setting and program the Power and PLL 830 * Control accordingly 831 */ 832 833 if (get_ref_clk() == 40) 834 ref_clk = REF_CLOCK_SPEED_40M; 835 else 836 ref_clk = PCIE_REF_CLOCK_SPEED_25M; 837 838 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 839 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 840 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 841 REG_16_BIT_MASK); 842 843 /* 9. Override Speed_PLL value and use MAC PLL */ 844 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 845 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 846 847 /* 10. Check the Polarity invert bit */ 848 data = 0U; 849 if (invert & COMPHY_POLARITY_TXD_INVERT) { 850 data |= TXD_INVERT_BIT; 851 } 852 if (invert & COMPHY_POLARITY_RXD_INVERT) { 853 data |= RXD_INVERT_BIT; 854 } 855 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 856 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); 857 858 /* 11. Release SW reset */ 859 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 860 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, 861 SOFT_RESET | MODE_REFDIV); 862 863 /* Wait for > 55 us to allow PCLK be enabled */ 864 udelay(PLL_SET_DELAY_US); 865 866 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, 867 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 868 COMPHY_PLL_TIMEOUT, REG_16BIT); 869 if (ret) 870 ERROR("Failed to lock PCIE PLL\n"); 871 872 debug_exit(); 873 874 return ret; 875 } 876 877 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 878 { 879 int mode = COMPHY_GET_MODE(comphy_mode); 880 int ret = 0; 881 882 debug_enter(); 883 884 switch (mode) { 885 case(COMPHY_SATA_MODE): 886 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 887 comphy_mode); 888 break; 889 case(COMPHY_SGMII_MODE): 890 case(COMPHY_2500BASEX_MODE): 891 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 892 comphy_mode); 893 break; 894 case (COMPHY_USB3_MODE): 895 case (COMPHY_USB3H_MODE): 896 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 897 comphy_mode); 898 break; 899 case (COMPHY_PCIE_MODE): 900 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 901 comphy_mode); 902 break; 903 default: 904 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 905 ret = -EINVAL; 906 break; 907 } 908 909 debug_exit(); 910 911 return ret; 912 } 913 914 static int mvebu_a3700_comphy_usb3_power_off(void) 915 { 916 /* 917 * Currently the USB3 MAC will control the USB3 PHY to set it to low 918 * state, thus do not need to power off USB3 PHY again. 919 */ 920 debug_enter(); 921 debug_exit(); 922 923 return 0; 924 } 925 926 static int mvebu_a3700_comphy_sata_power_off(void) 927 { 928 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 929 uint32_t offset; 930 931 debug_enter(); 932 933 /* Set phy isolation mode */ 934 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 935 comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 936 PHY_ISOLATE_MODE); 937 938 /* Power off PLL, Tx, Rx */ 939 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 940 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, 941 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 942 943 debug_exit(); 944 945 return 0; 946 } 947 948 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 949 { 950 int mode = COMPHY_GET_MODE(comphy_mode); 951 int err = 0; 952 953 debug_enter(); 954 955 if (!mode) { 956 /* 957 * The user did not specify which mode should be powered off. 958 * In this case we can identify this by reading the phy selector 959 * register. 960 */ 961 mode = mvebu_a3700_comphy_get_mode(comphy_index); 962 } 963 964 switch (mode) { 965 case(COMPHY_SGMII_MODE): 966 case(COMPHY_2500BASEX_MODE): 967 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index); 968 break; 969 case (COMPHY_USB3_MODE): 970 case (COMPHY_USB3H_MODE): 971 err = mvebu_a3700_comphy_usb3_power_off(); 972 break; 973 case (COMPHY_SATA_MODE): 974 err = mvebu_a3700_comphy_sata_power_off(); 975 break; 976 977 default: 978 debug("comphy%d: power off is not implemented for mode %d\n", 979 comphy_index, mode); 980 break; 981 } 982 983 debug_exit(); 984 985 return err; 986 } 987 988 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 989 { 990 uint32_t data, addr; 991 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 992 int ret = 0; 993 994 debug_enter(); 995 996 /* Polling status */ 997 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 998 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 999 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 1000 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 1001 COMPHY_PLL_TIMEOUT, REG_32BIT); 1002 1003 if (data != 0) { 1004 ERROR("TX PLL is not locked\n"); 1005 ret = -ETIMEDOUT; 1006 } 1007 1008 debug_exit(); 1009 1010 return ret; 1011 } 1012 1013 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 1014 { 1015 int mode = COMPHY_GET_MODE(comphy_mode); 1016 int ret = 0; 1017 1018 debug_enter(); 1019 1020 switch (mode) { 1021 case(COMPHY_SATA_MODE): 1022 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 1023 break; 1024 1025 default: 1026 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 1027 comphy_index, mode); 1028 ret = -EINVAL; 1029 break; 1030 } 1031 1032 debug_exit(); 1033 1034 return ret; 1035 } 1036