1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key hash lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 /* The first 4KB of Trusted SRAM are used as shared memory */ 62 #ifdef __PLAT_ARM_TRUSTED_SRAM_BASE__ 63 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 64 #else 65 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 66 #endif /* __PLAT_ARM_TRUSTED_SRAM_BASE__ */ 67 68 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 69 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 70 71 /* The remaining Trusted SRAM is used to load the BL images */ 72 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 73 ARM_SHARED_RAM_SIZE) 74 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 75 ARM_SHARED_RAM_SIZE) 76 77 /* 78 * The top 16MB of DRAM1 is configured as secure access only using the TZC 79 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 80 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 81 */ 82 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 83 84 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 85 ARM_DRAM1_SIZE - \ 86 ARM_SCP_TZC_DRAM1_SIZE) 87 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 88 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 89 ARM_SCP_TZC_DRAM1_SIZE - 1U) 90 91 /* 92 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 93 * firmware. This region is meant to be NOLOAD and will not be zero 94 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 95 * placed here. 96 */ 97 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 98 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 99 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 100 ARM_EL3_TZC_DRAM1_SIZE - 1U) 101 102 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 103 ARM_DRAM1_SIZE - \ 104 ARM_TZC_DRAM1_SIZE) 105 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 106 (ARM_SCP_TZC_DRAM1_SIZE + \ 107 ARM_EL3_TZC_DRAM1_SIZE)) 108 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 109 ARM_AP_TZC_DRAM1_SIZE - 1U) 110 111 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 112 #if ARM_CRYPTOCELL_INTEG 113 /* 114 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 115 * This is required by CryptoCell to authenticate BL33 which is loaded 116 * into the Non Secure DDR. 117 */ 118 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 119 #else 120 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 121 #endif 122 123 #ifdef SPD_opteed 124 /* 125 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 126 * load/authenticate the trusted os extra image. The first 512KB of 127 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 128 * for OPTEE is paged image which only include the paging part using 129 * virtual memory but without "init" data. OPTEE will copy the "init" data 130 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 131 * extra image behind the "init" data. 132 */ 133 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 134 ARM_AP_TZC_DRAM1_SIZE - \ 135 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 136 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 137 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 138 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 139 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 140 MT_MEMORY | MT_RW | MT_SECURE) 141 142 /* 143 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 144 * support is enabled). 145 */ 146 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 147 BL32_BASE, \ 148 BL32_LIMIT - BL32_BASE, \ 149 MT_MEMORY | MT_RW | MT_SECURE) 150 #endif /* SPD_opteed */ 151 152 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 153 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 154 ARM_TZC_DRAM1_SIZE) 155 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 156 ARM_NS_DRAM1_SIZE - 1U) 157 #ifdef __PLAT_ARM_DRAM1_BASE__ 158 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 159 #else 160 #define ARM_DRAM1_BASE ULL(0x80000000) 161 #endif /* __PLAT_ARM_DRAM1_BASE__ */ 162 163 #define ARM_DRAM1_SIZE ULL(0x80000000) 164 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 165 ARM_DRAM1_SIZE - 1U) 166 167 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 168 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 169 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 170 ARM_DRAM2_SIZE - 1U) 171 172 #define ARM_IRQ_SEC_PHY_TIMER 29 173 174 #define ARM_IRQ_SEC_SGI_0 8 175 #define ARM_IRQ_SEC_SGI_1 9 176 #define ARM_IRQ_SEC_SGI_2 10 177 #define ARM_IRQ_SEC_SGI_3 11 178 #define ARM_IRQ_SEC_SGI_4 12 179 #define ARM_IRQ_SEC_SGI_5 13 180 #define ARM_IRQ_SEC_SGI_6 14 181 #define ARM_IRQ_SEC_SGI_7 15 182 183 /* 184 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 185 * terminology. On a GICv2 system or mode, the lists will be merged and treated 186 * as Group 0 interrupts. 187 */ 188 #define ARM_G1S_IRQ_PROPS(grp) \ 189 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 190 GIC_INTR_CFG_LEVEL), \ 191 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 192 GIC_INTR_CFG_EDGE), \ 193 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 194 GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 196 GIC_INTR_CFG_EDGE), \ 197 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 198 GIC_INTR_CFG_EDGE), \ 199 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 200 GIC_INTR_CFG_EDGE), \ 201 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 202 GIC_INTR_CFG_EDGE) 203 204 #define ARM_G0_IRQ_PROPS(grp) \ 205 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 206 GIC_INTR_CFG_EDGE), \ 207 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 208 GIC_INTR_CFG_EDGE) 209 210 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 211 ARM_SHARED_RAM_BASE, \ 212 ARM_SHARED_RAM_SIZE, \ 213 MT_DEVICE | MT_RW | MT_SECURE) 214 215 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 216 ARM_NS_DRAM1_BASE, \ 217 ARM_NS_DRAM1_SIZE, \ 218 MT_MEMORY | MT_RW | MT_NS) 219 220 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 221 ARM_DRAM2_BASE, \ 222 ARM_DRAM2_SIZE, \ 223 MT_MEMORY | MT_RW | MT_NS) 224 225 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 226 TSP_SEC_MEM_BASE, \ 227 TSP_SEC_MEM_SIZE, \ 228 MT_MEMORY | MT_RW | MT_SECURE) 229 230 #if ARM_BL31_IN_DRAM 231 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 232 BL31_BASE, \ 233 PLAT_ARM_MAX_BL31_SIZE, \ 234 MT_MEMORY | MT_RW | MT_SECURE) 235 #endif 236 237 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 238 ARM_EL3_TZC_DRAM1_BASE, \ 239 ARM_EL3_TZC_DRAM1_SIZE, \ 240 MT_MEMORY | MT_RW | MT_SECURE) 241 242 #if defined(SPD_spmd) 243 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 244 PLAT_ARM_TRUSTED_DRAM_BASE, \ 245 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 246 MT_MEMORY | MT_RW | MT_SECURE) 247 #endif 248 249 250 /* 251 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 252 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 253 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 254 * to be able to access the heap. 255 */ 256 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 257 BL1_RW_BASE, \ 258 BL1_RW_LIMIT - BL1_RW_BASE, \ 259 MT_MEMORY | MT_RW | MT_SECURE) 260 261 /* 262 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 263 * otherwise one region is defined containing both. 264 */ 265 #if SEPARATE_CODE_AND_RODATA 266 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 267 BL_CODE_BASE, \ 268 BL_CODE_END - BL_CODE_BASE, \ 269 MT_CODE | MT_SECURE), \ 270 MAP_REGION_FLAT( \ 271 BL_RO_DATA_BASE, \ 272 BL_RO_DATA_END \ 273 - BL_RO_DATA_BASE, \ 274 MT_RO_DATA | MT_SECURE) 275 #else 276 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 277 BL_CODE_BASE, \ 278 BL_CODE_END - BL_CODE_BASE, \ 279 MT_CODE | MT_SECURE) 280 #endif 281 #if USE_COHERENT_MEM 282 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 283 BL_COHERENT_RAM_BASE, \ 284 BL_COHERENT_RAM_END \ 285 - BL_COHERENT_RAM_BASE, \ 286 MT_DEVICE | MT_RW | MT_SECURE) 287 #endif 288 #if USE_ROMLIB 289 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 290 ROMLIB_RO_BASE, \ 291 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 292 MT_CODE | MT_SECURE) 293 294 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 295 ROMLIB_RW_BASE, \ 296 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 297 MT_MEMORY | MT_RW | MT_SECURE) 298 #endif 299 300 /* 301 * Map mem_protect flash region with read and write permissions 302 */ 303 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 304 V2M_FLASH_BLOCK_SIZE, \ 305 MT_DEVICE | MT_RW | MT_SECURE) 306 /* 307 * Map the region for device tree configuration with read and write permissions 308 */ 309 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 310 (ARM_FW_CONFIGS_LIMIT \ 311 - ARM_BL_RAM_BASE), \ 312 MT_MEMORY | MT_RW | MT_SECURE) 313 314 /* 315 * The max number of regions like RO(code), coherent and data required by 316 * different BL stages which need to be mapped in the MMU. 317 */ 318 #define ARM_BL_REGIONS 6 319 320 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 321 ARM_BL_REGIONS) 322 323 /* Memory mapped Generic timer interfaces */ 324 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 325 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 326 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 327 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 328 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 329 330 #define ARM_CONSOLE_BAUDRATE 115200 331 332 /* Trusted Watchdog constants */ 333 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 334 #define ARM_SP805_TWDG_CLK_HZ 32768 335 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 336 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 337 #define ARM_TWDG_TIMEOUT_SEC 128 338 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 339 ARM_TWDG_TIMEOUT_SEC) 340 341 /****************************************************************************** 342 * Required platform porting definitions common to all ARM standard platforms 343 *****************************************************************************/ 344 345 /* 346 * This macro defines the deepest retention state possible. A higher state 347 * id will represent an invalid or a power down state. 348 */ 349 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 350 351 /* 352 * This macro defines the deepest power down states possible. Any state ID 353 * higher than this is invalid. 354 */ 355 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 356 357 /* 358 * Some data must be aligned on the biggest cache line size in the platform. 359 * This is known only to the platform as it might have a combination of 360 * integrated and external caches. 361 */ 362 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 363 364 /* 365 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 366 * and limit. Leave enough space of BL2 meminfo. 367 */ 368 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 369 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 370 + (PAGE_SIZE / 2U)) 371 372 /* 373 * Boot parameters passed from BL2 to BL31/BL32 are stored here 374 */ 375 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 376 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 377 + (PAGE_SIZE / 2U)) 378 379 /* 380 * Define limit of firmware configuration memory: 381 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 382 */ 383 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 384 385 /******************************************************************************* 386 * BL1 specific defines. 387 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 388 * addresses. 389 ******************************************************************************/ 390 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 391 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 392 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 393 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 394 /* 395 * Put BL1 RW at the top of the Trusted SRAM. 396 */ 397 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 398 ARM_BL_RAM_SIZE - \ 399 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 400 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 401 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 402 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 403 404 #define ROMLIB_RO_BASE BL1_RO_LIMIT 405 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 406 407 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 408 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 409 410 /******************************************************************************* 411 * BL2 specific defines. 412 ******************************************************************************/ 413 #if BL2_AT_EL3 414 /* Put BL2 towards the middle of the Trusted SRAM */ 415 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 416 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 417 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 418 419 #else 420 /* 421 * Put BL2 just below BL1. 422 */ 423 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 424 #define BL2_LIMIT BL1_RW_BASE 425 #endif 426 427 /******************************************************************************* 428 * BL31 specific defines. 429 ******************************************************************************/ 430 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 431 /* 432 * Put BL31 at the bottom of TZC secured DRAM 433 */ 434 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 435 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 436 PLAT_ARM_MAX_BL31_SIZE) 437 /* 438 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 439 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 440 */ 441 #if SEPARATE_NOBITS_REGION 442 #define BL31_NOBITS_BASE BL2_BASE 443 #define BL31_NOBITS_LIMIT BL2_LIMIT 444 #endif /* SEPARATE_NOBITS_REGION */ 445 #elif (RESET_TO_BL31) 446 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 447 # if !ENABLE_PIE 448 # error "BL31 must be a PIE if RESET_TO_BL31=1." 449 #endif 450 /* 451 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 452 * used for building BL31 and not used for loading BL31. 453 */ 454 # define BL31_BASE 0x0 455 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 456 #else 457 /* Put BL31 below BL2 in the Trusted SRAM.*/ 458 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 459 - PLAT_ARM_MAX_BL31_SIZE) 460 #define BL31_PROGBITS_LIMIT BL2_BASE 461 /* 462 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 463 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 464 */ 465 #if BL2_AT_EL3 466 #define BL31_LIMIT BL2_BASE 467 #else 468 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 469 #endif 470 #endif 471 472 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 473 /******************************************************************************* 474 * BL32 specific defines for EL3 runtime in AArch32 mode 475 ******************************************************************************/ 476 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 477 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 478 # if !ENABLE_PIE 479 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 480 #endif 481 /* 482 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 483 * used for building BL32 and not used for loading BL32. 484 */ 485 # define BL32_BASE 0x0 486 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 487 # else 488 /* Put BL32 below BL2 in the Trusted SRAM.*/ 489 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 490 - PLAT_ARM_MAX_BL32_SIZE) 491 # define BL32_PROGBITS_LIMIT BL2_BASE 492 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 493 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 494 495 #else 496 /******************************************************************************* 497 * BL32 specific defines for EL3 runtime in AArch64 mode 498 ******************************************************************************/ 499 /* 500 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 501 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 502 * controller. 503 */ 504 # if SPM_MM 505 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 506 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 507 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 508 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 509 ARM_AP_TZC_DRAM1_SIZE) 510 # elif defined(SPD_spmd) 511 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 512 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 513 # define BL32_BASE PLAT_ARM_SPMC_BASE 514 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 515 PLAT_ARM_SPMC_SIZE) 516 # elif ARM_BL31_IN_DRAM 517 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 518 PLAT_ARM_MAX_BL31_SIZE) 519 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 520 PLAT_ARM_MAX_BL31_SIZE) 521 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 522 PLAT_ARM_MAX_BL31_SIZE) 523 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 524 ARM_AP_TZC_DRAM1_SIZE) 525 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 526 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 527 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 528 # define TSP_PROGBITS_LIMIT BL31_BASE 529 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 530 # define BL32_LIMIT BL31_BASE 531 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 532 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 533 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 534 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 535 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 536 + (UL(1) << 21)) 537 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 538 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 539 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 540 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 541 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 542 ARM_AP_TZC_DRAM1_SIZE) 543 # else 544 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 545 # endif 546 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 547 548 /* 549 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 550 * SPD and no SPM-MM, as they are the only ones that can be used as BL32. 551 */ 552 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 553 # if defined(SPD_none) && !SPM_MM 554 # undef BL32_BASE 555 # endif /* defined(SPD_none) && !SPM_MM */ 556 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 557 558 /******************************************************************************* 559 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 560 ******************************************************************************/ 561 #define BL2U_BASE BL2_BASE 562 #define BL2U_LIMIT BL2_LIMIT 563 564 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 565 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 566 567 /* 568 * ID of the secure physical generic timer interrupt used by the TSP. 569 */ 570 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 571 572 573 /* 574 * One cache line needed for bakery locks on ARM platforms 575 */ 576 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 577 578 /* Priority levels for ARM platforms */ 579 #define PLAT_RAS_PRI 0x10 580 #define PLAT_SDEI_CRITICAL_PRI 0x60 581 #define PLAT_SDEI_NORMAL_PRI 0x70 582 583 /* ARM platforms use 3 upper bits of secure interrupt priority */ 584 #define PLAT_PRI_BITS 3 585 586 /* SGI used for SDEI signalling */ 587 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 588 589 #if SDEI_IN_FCONF 590 /* ARM SDEI dynamic private event max count */ 591 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 592 593 /* ARM SDEI dynamic shared event max count */ 594 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 595 #else 596 /* ARM SDEI dynamic private event numbers */ 597 #define ARM_SDEI_DP_EVENT_0 1000 598 #define ARM_SDEI_DP_EVENT_1 1001 599 #define ARM_SDEI_DP_EVENT_2 1002 600 601 /* ARM SDEI dynamic shared event numbers */ 602 #define ARM_SDEI_DS_EVENT_0 2000 603 #define ARM_SDEI_DS_EVENT_1 2001 604 #define ARM_SDEI_DS_EVENT_2 2002 605 606 #define ARM_SDEI_PRIVATE_EVENTS \ 607 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 608 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 609 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 610 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 611 612 #define ARM_SDEI_SHARED_EVENTS \ 613 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 614 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 615 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 616 #endif /* SDEI_IN_FCONF */ 617 618 #endif /* ARM_DEF_H */ 619