1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key hash lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 62 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 63 #else 64 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 65 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 66 67 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 68 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 69 70 /* The remaining Trusted SRAM is used to load the BL images */ 71 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 72 ARM_SHARED_RAM_SIZE) 73 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 74 ARM_SHARED_RAM_SIZE) 75 76 /* 77 * The top 16MB of DRAM1 is configured as secure access only using the TZC 78 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 79 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 80 */ 81 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 82 83 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 84 ARM_DRAM1_SIZE - \ 85 ARM_SCP_TZC_DRAM1_SIZE) 86 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 87 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 88 ARM_SCP_TZC_DRAM1_SIZE - 1U) 89 90 /* 91 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 92 * firmware. This region is meant to be NOLOAD and will not be zero 93 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 94 * placed here. 95 */ 96 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 97 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 98 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 99 ARM_EL3_TZC_DRAM1_SIZE - 1U) 100 101 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 102 ARM_DRAM1_SIZE - \ 103 ARM_TZC_DRAM1_SIZE) 104 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 105 (ARM_SCP_TZC_DRAM1_SIZE + \ 106 ARM_EL3_TZC_DRAM1_SIZE)) 107 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 108 ARM_AP_TZC_DRAM1_SIZE - 1U) 109 110 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 111 #if ARM_CRYPTOCELL_INTEG 112 /* 113 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 114 * This is required by CryptoCell to authenticate BL33 which is loaded 115 * into the Non Secure DDR. 116 */ 117 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 118 #else 119 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 120 #endif 121 122 #ifdef SPD_opteed 123 /* 124 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 125 * load/authenticate the trusted os extra image. The first 512KB of 126 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 127 * for OPTEE is paged image which only include the paging part using 128 * virtual memory but without "init" data. OPTEE will copy the "init" data 129 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 130 * extra image behind the "init" data. 131 */ 132 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 133 ARM_AP_TZC_DRAM1_SIZE - \ 134 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 135 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 136 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 137 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 138 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 139 MT_MEMORY | MT_RW | MT_SECURE) 140 141 /* 142 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 143 * support is enabled). 144 */ 145 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 146 BL32_BASE, \ 147 BL32_LIMIT - BL32_BASE, \ 148 MT_MEMORY | MT_RW | MT_SECURE) 149 #endif /* SPD_opteed */ 150 151 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 152 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 153 ARM_TZC_DRAM1_SIZE) 154 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 155 ARM_NS_DRAM1_SIZE - 1U) 156 #ifdef PLAT_ARM_DRAM1_BASE 157 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 158 #else 159 #define ARM_DRAM1_BASE ULL(0x80000000) 160 #endif /* PLAT_ARM_DRAM1_BASE */ 161 162 #define ARM_DRAM1_SIZE ULL(0x80000000) 163 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 164 ARM_DRAM1_SIZE - 1U) 165 166 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 167 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 168 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 169 ARM_DRAM2_SIZE - 1U) 170 171 #define ARM_IRQ_SEC_PHY_TIMER 29 172 173 #define ARM_IRQ_SEC_SGI_0 8 174 #define ARM_IRQ_SEC_SGI_1 9 175 #define ARM_IRQ_SEC_SGI_2 10 176 #define ARM_IRQ_SEC_SGI_3 11 177 #define ARM_IRQ_SEC_SGI_4 12 178 #define ARM_IRQ_SEC_SGI_5 13 179 #define ARM_IRQ_SEC_SGI_6 14 180 #define ARM_IRQ_SEC_SGI_7 15 181 182 /* 183 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 184 * terminology. On a GICv2 system or mode, the lists will be merged and treated 185 * as Group 0 interrupts. 186 */ 187 #define ARM_G1S_IRQ_PROPS(grp) \ 188 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 189 GIC_INTR_CFG_LEVEL), \ 190 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 191 GIC_INTR_CFG_EDGE), \ 192 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 193 GIC_INTR_CFG_EDGE), \ 194 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 195 GIC_INTR_CFG_EDGE), \ 196 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 197 GIC_INTR_CFG_EDGE), \ 198 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 199 GIC_INTR_CFG_EDGE), \ 200 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 201 GIC_INTR_CFG_EDGE) 202 203 #define ARM_G0_IRQ_PROPS(grp) \ 204 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 205 GIC_INTR_CFG_EDGE), \ 206 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 207 GIC_INTR_CFG_EDGE) 208 209 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 210 ARM_SHARED_RAM_BASE, \ 211 ARM_SHARED_RAM_SIZE, \ 212 MT_DEVICE | MT_RW | MT_SECURE) 213 214 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 215 ARM_NS_DRAM1_BASE, \ 216 ARM_NS_DRAM1_SIZE, \ 217 MT_MEMORY | MT_RW | MT_NS) 218 219 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 220 ARM_DRAM2_BASE, \ 221 ARM_DRAM2_SIZE, \ 222 MT_MEMORY | MT_RW | MT_NS) 223 224 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 225 TSP_SEC_MEM_BASE, \ 226 TSP_SEC_MEM_SIZE, \ 227 MT_MEMORY | MT_RW | MT_SECURE) 228 229 #if ARM_BL31_IN_DRAM 230 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 231 BL31_BASE, \ 232 PLAT_ARM_MAX_BL31_SIZE, \ 233 MT_MEMORY | MT_RW | MT_SECURE) 234 #endif 235 236 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 237 ARM_EL3_TZC_DRAM1_BASE, \ 238 ARM_EL3_TZC_DRAM1_SIZE, \ 239 MT_MEMORY | MT_RW | MT_SECURE) 240 241 #if defined(SPD_spmd) 242 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 243 PLAT_ARM_TRUSTED_DRAM_BASE, \ 244 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 245 MT_MEMORY | MT_RW | MT_SECURE) 246 #endif 247 248 249 /* 250 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 251 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 252 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 253 * to be able to access the heap. 254 */ 255 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 256 BL1_RW_BASE, \ 257 BL1_RW_LIMIT - BL1_RW_BASE, \ 258 MT_MEMORY | MT_RW | MT_SECURE) 259 260 /* 261 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 262 * otherwise one region is defined containing both. 263 */ 264 #if SEPARATE_CODE_AND_RODATA 265 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 266 BL_CODE_BASE, \ 267 BL_CODE_END - BL_CODE_BASE, \ 268 MT_CODE | MT_SECURE), \ 269 MAP_REGION_FLAT( \ 270 BL_RO_DATA_BASE, \ 271 BL_RO_DATA_END \ 272 - BL_RO_DATA_BASE, \ 273 MT_RO_DATA | MT_SECURE) 274 #else 275 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 276 BL_CODE_BASE, \ 277 BL_CODE_END - BL_CODE_BASE, \ 278 MT_CODE | MT_SECURE) 279 #endif 280 #if USE_COHERENT_MEM 281 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 282 BL_COHERENT_RAM_BASE, \ 283 BL_COHERENT_RAM_END \ 284 - BL_COHERENT_RAM_BASE, \ 285 MT_DEVICE | MT_RW | MT_SECURE) 286 #endif 287 #if USE_ROMLIB 288 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 289 ROMLIB_RO_BASE, \ 290 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 291 MT_CODE | MT_SECURE) 292 293 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 294 ROMLIB_RW_BASE, \ 295 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 296 MT_MEMORY | MT_RW | MT_SECURE) 297 #endif 298 299 /* 300 * Map mem_protect flash region with read and write permissions 301 */ 302 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 303 V2M_FLASH_BLOCK_SIZE, \ 304 MT_DEVICE | MT_RW | MT_SECURE) 305 /* 306 * Map the region for device tree configuration with read and write permissions 307 */ 308 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 309 (ARM_FW_CONFIGS_LIMIT \ 310 - ARM_BL_RAM_BASE), \ 311 MT_MEMORY | MT_RW | MT_SECURE) 312 313 /* 314 * The max number of regions like RO(code), coherent and data required by 315 * different BL stages which need to be mapped in the MMU. 316 */ 317 #define ARM_BL_REGIONS 6 318 319 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 320 ARM_BL_REGIONS) 321 322 /* Memory mapped Generic timer interfaces */ 323 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 324 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 325 #else 326 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 327 #endif 328 329 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 330 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 331 #else 332 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 333 #endif 334 335 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 336 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 337 #else 338 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 339 #endif 340 341 #ifdef PLAT_ARM_SYS_CNT_BASE_S 342 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 343 #else 344 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 345 #endif 346 347 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 348 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 349 #else 350 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 351 #endif 352 353 #define ARM_CONSOLE_BAUDRATE 115200 354 355 /* Trusted Watchdog constants */ 356 #ifdef PLAT_ARM_SP805_TWDG_BASE 357 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 358 #else 359 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 360 #endif 361 #define ARM_SP805_TWDG_CLK_HZ 32768 362 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 363 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 364 #define ARM_TWDG_TIMEOUT_SEC 128 365 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 366 ARM_TWDG_TIMEOUT_SEC) 367 368 /****************************************************************************** 369 * Required platform porting definitions common to all ARM standard platforms 370 *****************************************************************************/ 371 372 /* 373 * This macro defines the deepest retention state possible. A higher state 374 * id will represent an invalid or a power down state. 375 */ 376 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 377 378 /* 379 * This macro defines the deepest power down states possible. Any state ID 380 * higher than this is invalid. 381 */ 382 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 383 384 /* 385 * Some data must be aligned on the biggest cache line size in the platform. 386 * This is known only to the platform as it might have a combination of 387 * integrated and external caches. 388 */ 389 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 390 391 /* 392 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 393 * and limit. Leave enough space of BL2 meminfo. 394 */ 395 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 396 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 397 + (PAGE_SIZE / 2U)) 398 399 /* 400 * Boot parameters passed from BL2 to BL31/BL32 are stored here 401 */ 402 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 403 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 404 + (PAGE_SIZE / 2U)) 405 406 /* 407 * Define limit of firmware configuration memory: 408 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 409 */ 410 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 411 412 /******************************************************************************* 413 * BL1 specific defines. 414 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 415 * addresses. 416 ******************************************************************************/ 417 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 418 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 419 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 420 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 421 /* 422 * Put BL1 RW at the top of the Trusted SRAM. 423 */ 424 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 425 ARM_BL_RAM_SIZE - \ 426 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 427 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 428 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 429 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 430 431 #define ROMLIB_RO_BASE BL1_RO_LIMIT 432 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 433 434 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 435 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 436 437 /******************************************************************************* 438 * BL2 specific defines. 439 ******************************************************************************/ 440 #if BL2_AT_EL3 441 /* Put BL2 towards the middle of the Trusted SRAM */ 442 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 443 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 444 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 445 446 #else 447 /* 448 * Put BL2 just below BL1. 449 */ 450 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 451 #define BL2_LIMIT BL1_RW_BASE 452 #endif 453 454 /******************************************************************************* 455 * BL31 specific defines. 456 ******************************************************************************/ 457 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 458 /* 459 * Put BL31 at the bottom of TZC secured DRAM 460 */ 461 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 462 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 463 PLAT_ARM_MAX_BL31_SIZE) 464 /* 465 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 466 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 467 */ 468 #if SEPARATE_NOBITS_REGION 469 #define BL31_NOBITS_BASE BL2_BASE 470 #define BL31_NOBITS_LIMIT BL2_LIMIT 471 #endif /* SEPARATE_NOBITS_REGION */ 472 #elif (RESET_TO_BL31) 473 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 474 # if !ENABLE_PIE 475 # error "BL31 must be a PIE if RESET_TO_BL31=1." 476 #endif 477 /* 478 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 479 * used for building BL31 and not used for loading BL31. 480 */ 481 # define BL31_BASE 0x0 482 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 483 #else 484 /* Put BL31 below BL2 in the Trusted SRAM.*/ 485 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 486 - PLAT_ARM_MAX_BL31_SIZE) 487 #define BL31_PROGBITS_LIMIT BL2_BASE 488 /* 489 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 490 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 491 */ 492 #if BL2_AT_EL3 493 #define BL31_LIMIT BL2_BASE 494 #else 495 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 496 #endif 497 #endif 498 499 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 500 /******************************************************************************* 501 * BL32 specific defines for EL3 runtime in AArch32 mode 502 ******************************************************************************/ 503 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 504 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 505 # if !ENABLE_PIE 506 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 507 #endif 508 /* 509 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 510 * used for building BL32 and not used for loading BL32. 511 */ 512 # define BL32_BASE 0x0 513 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 514 # else 515 /* Put BL32 below BL2 in the Trusted SRAM.*/ 516 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 517 - PLAT_ARM_MAX_BL32_SIZE) 518 # define BL32_PROGBITS_LIMIT BL2_BASE 519 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 520 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 521 522 #else 523 /******************************************************************************* 524 * BL32 specific defines for EL3 runtime in AArch64 mode 525 ******************************************************************************/ 526 /* 527 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 528 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 529 * controller. 530 */ 531 # if SPM_MM 532 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 533 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 534 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 535 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 536 ARM_AP_TZC_DRAM1_SIZE) 537 # elif defined(SPD_spmd) 538 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 539 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 540 # define BL32_BASE PLAT_ARM_SPMC_BASE 541 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 542 PLAT_ARM_SPMC_SIZE) 543 # elif ARM_BL31_IN_DRAM 544 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 545 PLAT_ARM_MAX_BL31_SIZE) 546 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 547 PLAT_ARM_MAX_BL31_SIZE) 548 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 549 PLAT_ARM_MAX_BL31_SIZE) 550 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 551 ARM_AP_TZC_DRAM1_SIZE) 552 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 553 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 554 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 555 # define TSP_PROGBITS_LIMIT BL31_BASE 556 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 557 # define BL32_LIMIT BL31_BASE 558 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 559 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 560 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 561 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 562 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 563 + (UL(1) << 21)) 564 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 565 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 566 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 567 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 568 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 569 ARM_AP_TZC_DRAM1_SIZE) 570 # else 571 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 572 # endif 573 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 574 575 /* 576 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 577 * SPD and no SPM-MM, as they are the only ones that can be used as BL32. 578 */ 579 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 580 # if defined(SPD_none) && !SPM_MM 581 # undef BL32_BASE 582 # endif /* defined(SPD_none) && !SPM_MM */ 583 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 584 585 /******************************************************************************* 586 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 587 ******************************************************************************/ 588 #define BL2U_BASE BL2_BASE 589 #define BL2U_LIMIT BL2_LIMIT 590 591 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 592 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 593 594 /* 595 * ID of the secure physical generic timer interrupt used by the TSP. 596 */ 597 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 598 599 600 /* 601 * One cache line needed for bakery locks on ARM platforms 602 */ 603 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 604 605 /* Priority levels for ARM platforms */ 606 #define PLAT_RAS_PRI 0x10 607 #define PLAT_SDEI_CRITICAL_PRI 0x60 608 #define PLAT_SDEI_NORMAL_PRI 0x70 609 610 /* ARM platforms use 3 upper bits of secure interrupt priority */ 611 #define PLAT_PRI_BITS 3 612 613 /* SGI used for SDEI signalling */ 614 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 615 616 #if SDEI_IN_FCONF 617 /* ARM SDEI dynamic private event max count */ 618 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 619 620 /* ARM SDEI dynamic shared event max count */ 621 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 622 #else 623 /* ARM SDEI dynamic private event numbers */ 624 #define ARM_SDEI_DP_EVENT_0 1000 625 #define ARM_SDEI_DP_EVENT_1 1001 626 #define ARM_SDEI_DP_EVENT_2 1002 627 628 /* ARM SDEI dynamic shared event numbers */ 629 #define ARM_SDEI_DS_EVENT_0 2000 630 #define ARM_SDEI_DS_EVENT_1 2001 631 #define ARM_SDEI_DS_EVENT_2 2002 632 633 #define ARM_SDEI_PRIVATE_EVENTS \ 634 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 635 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 636 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 637 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 638 639 #define ARM_SDEI_SHARED_EVENTS \ 640 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 641 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 642 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 643 #endif /* SDEI_IN_FCONF */ 644 645 #endif /* ARM_DEF_H */ 646