feat(cpu): add support for Hayes CPU

This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use he

feat(cpu): add support for Hayes CPU

This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use here.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If0e0070cfa77fee8f6eebfee13d3c4f209ad84fc

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docs: armv8-R aarch64 fvp_r documentation

Documenting armv8-R aarch64 fvp_r features, boot sequence, and build
procedure.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I

docs: armv8-R aarch64 fvp_r documentation

Documenting armv8-R aarch64 fvp_r features, boot sequence, and build
procedure.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: If75d59acdf0f8a61cea6187967a4c35af2f31c98

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fvp_r: load, auth, and transfer from BL1 to BL33

Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrme

fvp_r: load, auth, and transfer from BL1 to BL33

Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40

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chore: fvp_r: Initial No-EL3 and MPU Implementation

For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.

Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac39

chore: fvp_r: Initial No-EL3 and MPU Implementation

For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.

Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac3915b982ad1e61d24365bdd1584b3070425

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fvp_r: initial platform port for fvp_r

Creating a platform port for FVP_R based on the FVP platform.
Differences including only-BL1, aarch64, Secure only, and EL2 being the
ELmax (No EL3).

Signed-o

fvp_r: initial platform port for fvp_r

Creating a platform port for FVP_R based on the FVP platform.
Differences including only-BL1, aarch64, Secure only, and EL2 being the
ELmax (No EL3).

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I1283e033fbd4e03c397d0a2c10c4139548b4eee4

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Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk)

Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk): update RCC registers file
fix(stm32mp1_clk): keep RTCAPB clock always on
fix(stm32mp1_clk): fix RTC clock rating
fix(stm32mp1_clk): correctly manage RTC clock source
fix(spi_nand): check correct manufacturer id
fix(spi_nand): check that parameters have been set

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fix(drivers/marvell/comphy-cp110): fix error code in pcie power on

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to er

fix(drivers/marvell/comphy-cp110): fix error code in pcie power on

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to error code
-ETIMEDOUT on error like it is done in other functions.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I16cac81bbcbe2113e139722dc0e8fc2b85428d1b

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fix(drivers/marvell/comphy-3700): handle failures in power functions

Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropr

fix(drivers/marvell/comphy-3700): handle failures in power functions

Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropriate error
code in return value.

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So return -ETIMEDOUT on error from power
functions like it is doing Marvell comphy-cp110 driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6c709c0c9616ab26829616a42a85b713f314b201

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fix(drivers/marvell/comphy-3700): fix address overflow

Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.

fix(drivers/marvell/comphy-3700): fix address overflow

Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.

Change type of 'offset' variables in mvebu_a3700_comphy_usb3_power_on()
and mvebu_a3700_comphy_sgmii_power_on() / off() functions to uintptr_t
as in this variable is stored physical address of registers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I69581714f8899d21cc1a27005747708f0f1cd933

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refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()

Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.

Remove pa

refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()

Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.

Remove parameter 'comphy_index' and instead of 32-bit variable 'mode',
pass only boolean value which represents 1 Gbps speed.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I018d158f689ddf7d1f57003717d709c00d988fba

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refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB

refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB 3.0 modes and remove additional
'mode' argument which is not needed anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I23146f569db318dbaed5d411d7d175abf6efff85

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Merge "errata: workaround for Cortex-A710 erratum 2083908" into integration

Merge changes If3859447,I56084c42 into integration

* changes:
feat(plat/arm/sgi): add CPU specific handler for Neoverse N2
feat(plat/arm/sgi): add CPU specific handler for Neoverse V1

feat(plat/arm/sgi): add CPU specific handler for Neoverse N2

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
S

feat(plat/arm/sgi): add CPU specific handler for Neoverse N2

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
So add Neoverse N2 CPU specific handler in platform reset handler to
clear the CORE_PWRDN_EN bit.

Signed-off-by: shriram.k <shriram.k@arm.com>
Change-Id: If3859447410c4b8e704588993941178fa9411f52

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feat(plat/arm/sgi): add CPU specific handler for Neoverse V1

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
S

feat(plat/arm/sgi): add CPU specific handler for Neoverse V1

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
So add Neoverse V1 CPU specific handler in platform reset handler to
clear the CORE_PWRDN_EN bit.

Signed-off-by: shriram.k <shriram.k@arm.com>
Change-Id: I56084c42a56c401503a751cb518238c83cfca8ac

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Merge "build(bl2): enable SP pkg loading for S-EL1 SPMC" into integration

fix(plat/mediatek/mt8183): fix out-of-bound access

Fix coverity checks which is found on:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1806/comment/eaec126f_af5eb624/

Change-Id: I

fix(plat/mediatek/mt8183): fix out-of-bound access

Fix coverity checks which is found on:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1806/comment/eaec126f_af5eb624/

Change-Id: I9405f7f67aa4115c1a7b8b4623b6b0830e62f814
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>

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Merge "feat(hcx): add build option to enable FEAT_HCX" into integration

build(bl2): enable SP pkg loading for S-EL1 SPMC

Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.

Signed-off-by: Balint Dobszay <balin

build(bl2): enable SP pkg loading for S-EL1 SPMC

Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.

Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: I5bf5a32248e85a26d0345cacff7d539eed824cfc

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Merge changes from topic "od/sp-uuid-gen" into integration

* changes:
fix: OP-TEE SP manifest per latest SPMC changes
fix: SP UUID little to big endian in TF-A build

fix: OP-TEE SP manifest per latest SPMC changes

Update UUID to little endian:
The SPMC expects a little endian representation of the UUID as an array
of four integers in the SP manifest.

Add manage

fix: OP-TEE SP manifest per latest SPMC changes

Update UUID to little endian:
The SPMC expects a little endian representation of the UUID as an array
of four integers in the SP manifest.

Add managed exit field and cosmetic comments updates.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icad93ca70bc27bc9d83b8cf888fe5f8839cb1288

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fix: SP UUID little to big endian in TF-A build

The UUID field in SP manifest DTS is represented as an array of four
integers that the SPMC consumes using the little endian representation.
The reaso

fix: SP UUID little to big endian in TF-A build

The UUID field in SP manifest DTS is represented as an array of four
integers that the SPMC consumes using the little endian representation.
The reason is that those values are directly mapped to the SMCCC section
5.3 recommendation and the way they are exposed to the
FFA_PARTITION_INFO_GET interface.

Per [1] TF-A build flow expects a big endian representation of the UUID
so the sp_mk_generator script is updated to accommodate this conversion.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9563

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7c7b295225e23ea64f49170e27d97442b289703b

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feat(plat/mediatek/common): enable software reset for CIRQ

CIRQ software reset can be used on all platforms, so we remove
CIRQ_NEED_SW_RESET in mt_cirq_sw_reset to enable software reset.

BUG=b:1922

feat(plat/mediatek/common): enable software reset for CIRQ

CIRQ software reset can be used on all platforms, so we remove
CIRQ_NEED_SW_RESET in mt_cirq_sw_reset to enable software reset.

BUG=b:192200380, b:201035723

Signed-off-by: Pan Gao <gtk_pangao@mediatek.com>
Change-Id: Id53ea099ae566bf2a573fca866bd10c60429bd5a

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feat(plat/mdeiatek/mt8195): add DFD control in SiP service

DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those

feat(plat/mdeiatek/mt8195): add DFD control in SiP service

DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.

BUG=b:192429713

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7

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feat(hcx): add build option to enable FEAT_HCX

FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn

feat(hcx): add build option to enable FEAT_HCX

FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit. This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b

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