Merge changes I573e6478,I52dc3bee,I7e543664 into integration

* changes:
feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
feat(gic600ae_fmu): disable SMID for unavailable blocks
feat(gic600ae_

Merge changes I573e6478,I52dc3bee,I7e543664 into integration

* changes:
feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
feat(gic600ae_fmu): disable SMID for unavailable blocks
feat(gic600ae_fmu): introduce support for RAS error handling

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chore(measured boot): remove unused DTC flags

We no longer need to pass special flags to the device tree compiler
for measured boot. These are a left over from the days where we used
to pass BL2 mea

chore(measured boot): remove unused DTC flags

We no longer need to pass special flags to the device tree compiler
for measured boot. These are a left over from the days where we used
to pass BL2 measurement to BL2 image via TB_FW configuration file.

This should have been removed as part of commit eab78e9ba4e36da27
("refactor(measured_boot): remove passing of BL2 hash via device
tree") but was missed at the time.

Change-Id: Iced7e60af7ca660c342c0fc3a33b51865d67f04d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge "build(changelog): add new scope for TI platform" into integration

feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs

The following SMIDs are disabled by default.

* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate overr

feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs

The following SMIDs are disabled by default.

* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate override
* ITS: MBIST REQ error and ITS FMU ClkGate override

This patch explicitly enables them during the FMU init sequence.

Change-Id: I573e64786e3318d4cbcd07d0a1caf25f8e6e9200
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "jc/detect_feat" into integration

* changes:
docs(build): update the feature enablement flags
refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags
re

Merge changes from topic "jc/detect_feat" into integration

* changes:
docs(build): update the feature enablement flags
refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags
refactor(el3-runtime): add arch-features detection mechanism

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Merge changes from topic "mapping" into integration

* changes:
feat(debug): update print_memory_map.py
feat(bl_common): add XLAT tables symbols in linker script

feat(debug): update print_memory_map.py

Add some entries in blx_symbols, that are used when the flag
SEPARATE_CODE_AND_RODATA is not enabled (__RO_* and __TEXT_RESIDENT_*).
Add all new symbols that

feat(debug): update print_memory_map.py

Add some entries in blx_symbols, that are used when the flag
SEPARATE_CODE_AND_RODATA is not enabled (__RO_* and __TEXT_RESIDENT_*).
Add all new symbols that were not yet present in the script.
Correct __BSS_END to __BSS_END__, and add __BSS_START__.
Add new *_XLAT_TABLE_* symbols.
As those strings are longer than 22, update display format string to
be dependent on the longest string.
The script also skips lines for which the _START__ and _END__
symbols have the same address (empty sections).

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I6c510ced6116b35d14ee2cb7a6711405604380d6

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feat(gic600ae_fmu): disable SMID for unavailable blocks

This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safet

feat(gic600ae_fmu): disable SMID for unavailable blocks

This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safety mechanisms for GIC-600AE are enabled by default and should be
disabled for blocks that are not present on the platform to avoid
false positive RAS errors.

Change-Id: I52dc3bee9a8b49fd2e51d7ed851fdc803a48e6e3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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feat(bl_common): add XLAT tables symbols in linker script

Add __BASE_XLAT_TABLE_START__/_END__ and __XLAT_TABLE_START__/_END__
symbols in the linker script to have them in the .map file.
This allows

feat(bl_common): add XLAT tables symbols in linker script

Add __BASE_XLAT_TABLE_START__/_END__ and __XLAT_TABLE_START__/_END__
symbols in the linker script to have them in the .map file.
This allows displaying those areas when running memory map script.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I768a459c5cecc403a9b81b36a71397ecc3179f4f

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feat(gic600ae_fmu): introduce support for RAS error handling

The GIC-600AE uses a range of RAS features for all RAMs, which include
SECDED, ECC, and Scrub, software and bus error reporting. The GIC

feat(gic600ae_fmu): introduce support for RAS error handling

The GIC-600AE uses a range of RAS features for all RAMs, which include
SECDED, ECC, and Scrub, software and bus error reporting. The GIC makes
all necessary information available to software through Armv8.2 RAS
architecture compliant register space.

This patch introduces support to probe the FMU_ERRGSR register to find
the right error record. Once the correct record is identified, the
"handler" function queries the FMU_ERR<m>STATUS register to further
identify the block ID, safety mechanism and the architecturally defined
primary error code. The description of the error is displayed on the
console to simplify debug.

Change-Id: I7e543664b74457afee2da250549f4c3d9beb1a03
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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docs(build): update the feature enablement flags

Adding the newly introduced build flags for feature enablement of the
following features:
1.FEAT_AMUv1p1 - ENABLE_FEAT_AMUv1p1
2.FEAT_CSV2_2 - ENABL

docs(build): update the feature enablement flags

Adding the newly introduced build flags for feature enablement of the
following features:
1.FEAT_AMUv1p1 - ENABLE_FEAT_AMUv1p1
2.FEAT_CSV2_2 - ENABLE_FEAT_CSV2_2
3.FEAT_VHE - ENABLE_FEAT_VHE
4.FEAT_DIT - ENABLE_FEAT_DIT
5.FEAT_SB - ENABLE_FEAT_SB
6.FEAT_SEL2 - ENABLE_FEAT_SEL2

Also as part of feature detection mechanism, we now support three
states for each of these features, allowing the flags to take either
(0 , 1 , 2) values. Henceforth the existing feature build options are
converted from boolean to numeric type and is updated accordingly
in this patch.

The build flags take a default value and will be internally enabled
when they become mandatory from a particular architecture version
and upwards. Platforms have the flexibility to overide this
internal enablement via this feature specific explicit build flags.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I0090c8c780c2e7d1a50ed9676983fe1df7a35e50

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fix(st-clock): correct stm32_clk_parse_fdt_by_name

The fdt_getprop() function sets the length to -1 if the property is not
found. We should then not use it later in stm32_clk_parse_fdt_by_name()
in

fix(st-clock): correct stm32_clk_parse_fdt_by_name

The fdt_getprop() function sets the length to -1 if the property is not
found. We should then not use it later in stm32_clk_parse_fdt_by_name()
in that case. Directly set *nb to 0U and return 0 if the property is not
found.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I19c5c953f392cdc768e0b1f3f240fc99a73a049c

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fix(st-clock): check _clk_stm32_get_parent return

This issue was found by Coverity (CID 376885). The _clk_stm32_get_parent()
return shouldn't be negative. Return the error in this case.

Signed-off-

fix(st-clock): check _clk_stm32_get_parent return

This issue was found by Coverity (CID 376885). The _clk_stm32_get_parent()
return shouldn't be negative. Return the error in this case.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I91eff7e99fcdac9a258100b163fd9b040a9bd2c0

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Merge "fix(st): remove extra chars from dtc version" into integration

fix(st): remove extra chars from dtc version

In some implementations of dtc tool (e.g. with yocto), there can be a 'v'
at the beginning of the version, and a '+' at the end. Just keep numbers
then,

fix(st): remove extra chars from dtc version

In some implementations of dtc tool (e.g. with yocto), there can be a 'v'
at the beginning of the version, and a '+' at the end. Just keep numbers
then, with a grep -o.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I180e97ab75ba3e5ceacb4b1961a1f22788b428a3

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feat(intel): add macro to switch between different UART PORT

HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using param

feat(intel): add macro to switch between different UART PORT

HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using parameter PLAT_INTEL_UART_BASE

This patch also fixing the plat_helpers.S where the
UART BASE is hardcoded to PLAT_UART0_BASE. It is then
switched to CRASH_CONSOLE_BASE.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f

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feat(intel): add SMC support for ROM Patch SHA384 mailbox

HSD #16014059592:
Add support for ROM Patch SHA384 mailbox SMC call.

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-

feat(intel): add SMC support for ROM Patch SHA384 mailbox

HSD #16014059592:
Add support for ROM Patch SHA384 mailbox SMC call.

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ide9a7af41a089980745cb7216a9bf85e7fbd84e3

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refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags

Replacing ARM_ARCH_AT_LEAST macro with feature specific build options
to prevent unconditional accesses to the registers during

refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags

Replacing ARM_ARCH_AT_LEAST macro with feature specific build options
to prevent unconditional accesses to the registers during context save
and restore routines.

Registers are tightly coupled with features more than architecture
versions. Henceforth having a feature-specific build flag guarding the
respective registers, will restrict any undefined actions.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I809774df580530803c8a6e05a62d8d4de0910e02

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refactor(el3-runtime): add arch-features detection mechanism

This patch adds architectural features detection procedure to ensure
features enabled are present in the given hardware implementation.

refactor(el3-runtime): add arch-features detection mechanism

This patch adds architectural features detection procedure to ensure
features enabled are present in the given hardware implementation.

It verifies whether the architecture build flags passed during
compilation match the respective features by reading their ID
registers. It reads through all the enabled feature specific ID
registers at once and panics in case of mismatch(feature enabled
but not implemented in PE).

Feature flags are used at sections (context_management,
save and restore routines of registers) during context switch.
If the enabled feature flag is not supported by the PE, it causes an
exception while saving or restoring the registers guarded by them.

With this mechanism, the build flags are validated at an early
phase prior to their usage, thereby preventing any undefined action
under their control.

This implementation is based on tristate approach for each feature and
currently FEAT_STATE=0 and FEAT_STATE=1 are covered as part of this
patch. FEAT_STATE=2 is planned for phase-2 implementation and will be
taken care separately.

The patch has been explicitly tested, by adding a new test_config
with build config enabling majority of the features and detected
all of them under FVP launched with parameters enabling v8.7 features.

Note: This is an experimental procedure and the mechanism itself is
guarded by a macro "FEATURE_DETECTION", which is currently being
disabled by default.

The "FEATURE_DETECTION" macro is documented and the platforms are
encouraged to make use of this diagnostic tool by enabling this
"FEATURE_DETECTION" flag explicitly and get used to its behaviour
during booting before the procedure gets mandated.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ia23d95430fe82d417a938b672bfb5edc401b0f43

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refactor(corstone700): namespace MHU driver filenames

There are plans to contribute a generic MHU driver to the TF-A code
base in the short term.

In preparation for this, rename the Corstone-700 MH

refactor(corstone700): namespace MHU driver filenames

There are plans to contribute a generic MHU driver to the TF-A code
base in the short term.

In preparation for this, rename the Corstone-700 MHU driver source
files and prefix them with the name of the platform to avoid any
ambiguity or name clashes with the upcoming generic MHU driver. Also
rename the header guard accordingly.

This renaming is inline with other platform-specific MHU drivers, such
as the ones used on Broadcom [1], Socionext [2] or Amlogic [3] platforms.

[1] plat/brcm/common/brcm_mhu.h
[2] plat/socionext/synquacer/drivers/mhu/sq_mhu.h
[3] plat/amlogic/common/aml_mhu.c

Change-Id: I8a5e5b16e7c19bf931a90422dfca8f6a2a0663b4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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fix(bl2): define RAM_NOLOAD for XIP

If BL2_IN_XIP_MEM is enabled, BL2 fails to compile because RAM_NOLOAD
symbol is not defined. As we could have a no-load region even if
BL2_IN_XIP_MEM is enabled,

fix(bl2): define RAM_NOLOAD for XIP

If BL2_IN_XIP_MEM is enabled, BL2 fails to compile because RAM_NOLOAD
symbol is not defined. As we could have a no-load region even if
BL2_IN_XIP_MEM is enabled, just put its definition outside the #if/#else
for this flag.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I9169ea799635f8a72790280f3f148d1cba4cd408

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style(plat/arm/corstone1000): resolve checkpatch warnings

Change-Id: Ic8cb9b0834806675c792018e809d7ba77fbe856f
Signed-off-by: David Vincze <david.vincze@arm.com>

feat(stm32mp1): retry 3 times FWU trial boot

If we reboot 3 times in trial mode, BL2 will select previous boot image.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Change-Id: I

feat(stm32mp1): retry 3 times FWU trial boot

If we reboot 3 times in trial mode, BL2 will select previous boot image.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Change-Id: I82b423cc84f0471fdb6fa7c393fc5fe411d25c06

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refactor(stm32mp1): update backup reg for FWU

Change the backup register used to store FWU parameters from 21 to 10.
This is chosen to have a Read/Write secure and Read non-secure register.
The mapp

refactor(stm32mp1): update backup reg for FWU

Change the backup register used to store FWU parameters from 21 to 10.
This is chosen to have a Read/Write secure and Read non-secure register.
The mapping is also changed: only the first 4 bits will be used to store
the FWU index. The 4 next bits will be used to store count info. The
other bits are reserved.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Change-Id: I9249768287ec5688ba2d8711ce04d429763543d7

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Merge changes I84e257b3,I1317e482 into integration

* changes:
fix(layerscape): fix coverity issue
fix(nxp-ddr): fix coverity issue