1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_MBOX_H 8 #define SOCFPGA_MBOX_H 9 10 #include <lib/utils_def.h> 11 12 13 #define MBOX_OFFSET 0xffa30000 14 15 #define MBOX_ATF_CLIENT_ID 0x1U 16 #define MBOX_MAX_JOB_ID 0xFU 17 #define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U) 18 #define MBOX_JOB_ID MBOX_MAX_JOB_ID 19 #define MBOX_TEST_BIT BIT(31) 20 21 /* Mailbox Shared Memory Register Map */ 22 #define MBOX_CIN 0x00 23 #define MBOX_ROUT 0x04 24 #define MBOX_URG 0x08 25 #define MBOX_INT 0x0C 26 #define MBOX_COUT 0x20 27 #define MBOX_RIN 0x24 28 #define MBOX_STATUS 0x2C 29 #define MBOX_CMD_BUFFER 0x40 30 #define MBOX_RESP_BUFFER 0xC0 31 32 /* Mailbox SDM doorbell */ 33 #define MBOX_DOORBELL_TO_SDM 0x400 34 #define MBOX_DOORBELL_FROM_SDM 0x480 35 36 37 /* Mailbox commands */ 38 39 #define MBOX_CMD_NOOP 0x00 40 #define MBOX_CMD_SYNC 0x01 41 #define MBOX_CMD_RESTART 0x02 42 #define MBOX_CMD_CANCEL 0x03 43 #define MBOX_CMD_VAB_SRC_CERT 0x0B 44 #define MBOX_CMD_GET_IDCODE 0x10 45 #define MBOX_CMD_GET_USERCODE 0x13 46 #define MBOX_CMD_GET_CHIPID 0x12 47 #define MBOX_CMD_REBOOT_HPS 0x47 48 49 /* Reconfiguration Commands */ 50 #define MBOX_CONFIG_STATUS 0x04 51 #define MBOX_RECONFIG 0x06 52 #define MBOX_RECONFIG_DATA 0x08 53 #define MBOX_RECONFIG_STATUS 0x09 54 55 /* HWMON Commands */ 56 #define MBOX_HWMON_READVOLT 0x18 57 #define MBOX_HWMON_READTEMP 0x19 58 59 60 /* QSPI Commands */ 61 #define MBOX_CMD_QSPI_OPEN 0x32 62 #define MBOX_CMD_QSPI_CLOSE 0x33 63 #define MBOX_CMD_QSPI_SET_CS 0x34 64 #define MBOX_CMD_QSPI_DIRECT 0x3B 65 66 /* RSU Commands */ 67 #define MBOX_GET_SUBPARTITION_TABLE 0x5A 68 #define MBOX_RSU_STATUS 0x5B 69 #define MBOX_RSU_UPDATE 0x5C 70 #define MBOX_HPS_STAGE_NOTIFY 0x5D 71 72 /* FCS Command */ 73 #define MBOX_FCS_GET_PROVISION 0x7B 74 #define MBOX_FCS_CNTR_SET_PREAUTH 0x7C 75 #define MBOX_FCS_ENCRYPT_REQ 0x7E 76 #define MBOX_FCS_DECRYPT_REQ 0x7F 77 #define MBOX_FCS_RANDOM_GEN 0x80 78 #define MBOX_FCS_OPEN_CS_SESSION 0xA0 79 #define MBOX_FCS_CLOSE_CS_SESSION 0xA1 80 81 /* PSG SIGMA Commands */ 82 #define MBOX_PSG_SIGMA_TEARDOWN 0xD5 83 84 /* Attestation Commands */ 85 #define MBOX_CREATE_CERT_ON_RELOAD 0x180 86 #define MBOX_GET_ATTESTATION_CERT 0x181 87 #define MBOX_ATTESTATION_SUBKEY 0x182 88 #define MBOX_GET_MEASUREMENT 0x183 89 90 /* Miscellaneous commands */ 91 #define MBOX_GET_ROM_PATCH_SHA384 0x1B0 92 93 /* Mailbox Definitions */ 94 95 #define CMD_DIRECT 0 96 #define CMD_INDIRECT 1 97 #define CMD_CASUAL 0 98 #define CMD_URGENT 1 99 100 #define MBOX_WORD_BYTE 4U 101 #define MBOX_RESP_BUFFER_SIZE 16 102 #define MBOX_CMD_BUFFER_SIZE 32 103 104 /* Execution states for HPS_STAGE_NOTIFY */ 105 #define HPS_EXECUTION_STATE_FSBL 0 106 #define HPS_EXECUTION_STATE_SSBL 1 107 #define HPS_EXECUTION_STATE_OS 2 108 109 /* Status Response */ 110 #define MBOX_RET_OK 0 111 #define MBOX_RET_ERROR -1 112 #define MBOX_NO_RESPONSE -2 113 #define MBOX_WRONG_ID -3 114 #define MBOX_BUFFER_FULL -4 115 #define MBOX_BUSY -5 116 #define MBOX_TIMEOUT -2047 117 118 /* Reconfig Status Response */ 119 #define RECONFIG_STATUS_STATE 0 120 #define RECONFIG_STATUS_PIN_STATUS 2 121 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 122 #define PIN_STATUS_NSTATUS (U(1) << 31) 123 #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) 124 #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) 125 #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) 126 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 127 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 128 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 129 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 130 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 131 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 132 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 133 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 134 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 135 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 136 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 137 138 139 /* Mailbox Macros */ 140 141 #define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \ 142 + MBOX_WORD_BYTE * (ptr)) 143 144 /* Mailbox interrupt flags and masks */ 145 #define MBOX_INT_FLAG_COE 0x1 146 #define MBOX_INT_FLAG_RIE 0x2 147 #define MBOX_INT_FLAG_UAE 0x100 148 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) 149 #define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) 150 151 /* Mailbox response and status */ 152 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x000007ff) 153 #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) 154 #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) 155 #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) 156 #define MBOX_STATUS_UA_MASK (1<<8) 157 158 /* Mailbox command and response */ 159 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) 160 #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) 161 #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) 162 #define MBOX_INDIRECT(val) ((val) << 11) 163 #define MBOX_CMD_MASK(header) ((header) & 0x7ff) 164 165 /* Mailbox payload */ 166 #define MBOX_DATA_MAX_LEN 0x3ff 167 #define MBOX_PAYLOAD_FLAG_BUSY BIT(0) 168 169 /* RSU Macros */ 170 #define RSU_VERSION_ACMF BIT(8) 171 #define RSU_VERSION_ACMF_MASK 0xff00 172 173 /* Config Status Macros */ 174 #define CONFIG_STATUS_WORD_SIZE 16U 175 #define CONFIG_STATUS_FW_VER_OFFSET 1 176 #define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF 177 178 /* Data structure */ 179 180 typedef struct mailbox_payload { 181 uint32_t header; 182 uint32_t data[MBOX_DATA_MAX_LEN]; 183 } mailbox_payload_t; 184 185 typedef struct mailbox_container { 186 uint32_t flag; 187 uint32_t index; 188 mailbox_payload_t *payload; 189 } mailbox_container_t; 190 191 /* Mailbox Function Definitions */ 192 193 void mailbox_set_int(uint32_t interrupt_input); 194 int mailbox_init(void); 195 void mailbox_set_qspi_close(void); 196 void mailbox_hps_qspi_enable(void); 197 198 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, 199 unsigned int len, uint32_t urgent, uint32_t *response, 200 unsigned int *resp_len); 201 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, 202 unsigned int len, unsigned int indirect); 203 int mailbox_read_response(uint32_t *job_id, uint32_t *response, 204 unsigned int *resp_len); 205 int mailbox_read_response_async(uint32_t *job_id, uint32_t *header, 206 uint32_t *response, unsigned int *resp_len, 207 uint8_t ignore_client_id); 208 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, 209 unsigned int *resp_len); 210 211 void mailbox_reset_cold(void); 212 void mailbox_clear_response(void); 213 214 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done); 215 int intel_mailbox_is_fpga_not_ready(void); 216 217 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); 218 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); 219 int mailbox_rsu_update(uint32_t *flash_offset); 220 int mailbox_hps_stage_notify(uint32_t execution_stage); 221 int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf); 222 int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf); 223 224 #endif /* SOCFPGA_MBOX_H */ 225