xref: /rk3399_ARM-atf/plat/intel/soc/common/include/socfpga_fcs.h (revision 537ff052579862a4865d36d06940feaa796d16da)
1 /*
2  * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOCFPGA_FCS_H
8 #define SOCFPGA_FCS_H
9 
10 /* FCS Definitions */
11 
12 #define FCS_RANDOM_WORD_SIZE			8U
13 #define FCS_PROV_DATA_WORD_SIZE			44U
14 #define FCS_SHA384_WORD_SIZE			12U
15 
16 #define FCS_RANDOM_BYTE_SIZE			(FCS_RANDOM_WORD_SIZE * 4U)
17 #define FCS_RANDOM_EXT_MAX_WORD_SIZE		1020U
18 #define FCS_PROV_DATA_BYTE_SIZE			(FCS_PROV_DATA_WORD_SIZE * 4U)
19 #define FCS_SHA384_BYTE_SIZE			(FCS_SHA384_WORD_SIZE * 4U)
20 
21 #define FCS_RANDOM_EXT_OFFSET			3
22 
23 #define FCS_MODE_DECRYPT			0x0
24 #define FCS_MODE_ENCRYPT			0x1
25 #define FCS_ENCRYPTION_DATA_0			0x10100
26 #define FCS_DECRYPTION_DATA_0			0x10102
27 #define FCS_OWNER_ID_OFFSET			0xC
28 #define FCS_CRYPTION_CRYPTO_HEADER		0x07000000
29 #define FCS_CRYPTION_RESP_WORD_SIZE		4U
30 #define FCS_CRYPTION_RESP_SIZE_OFFSET		3U
31 
32 #define PSGSIGMA_TEARDOWN_MAGIC			0xB852E2A4
33 #define	PSGSIGMA_SESSION_ID_ONE			0x1
34 #define PSGSIGMA_UNKNOWN_SESSION		0xFFFFFFFF
35 
36 #define	RESERVED_AS_ZERO			0x0
37 /* FCS Single cert */
38 
39 #define FCS_BIG_CNTR_SEL			0x1
40 
41 #define FCS_SVN_CNTR_0_SEL			0x2
42 #define FCS_SVN_CNTR_1_SEL			0x3
43 #define FCS_SVN_CNTR_2_SEL			0x4
44 #define FCS_SVN_CNTR_3_SEL			0x5
45 
46 #define FCS_BIG_CNTR_VAL_MAX			495U
47 #define FCS_SVN_CNTR_VAL_MAX			64U
48 
49 /* FCS Attestation Cert Request Parameter */
50 
51 #define FCS_ALIAS_CERT				0x01
52 #define FCS_DEV_ID_SELF_SIGN_CERT		0x02
53 #define FCS_DEV_ID_ENROLL_CERT			0x04
54 #define FCS_ENROLL_SELF_SIGN_CERT		0x08
55 #define FCS_PLAT_KEY_CERT			0x10
56 
57 /* FCS Crypto Service */
58 
59 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE		88U
60 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE		36U
61 #define FCS_CS_KEY_RESP_STATUS_MASK		0xFF
62 #define FCS_CS_KEY_RESP_STATUS_OFFSET		16U
63 
64 #define FCS_CS_FIELD_SIZE_MASK			0xFFFF
65 #define FCS_CS_FIELD_FLAG_OFFSET		24
66 #define FCS_CS_FIELD_FLAG_INIT			BIT(0)
67 #define FCS_CS_FIELD_FLAG_UPDATE		BIT(1)
68 #define FCS_CS_FIELD_FLAG_FINALIZE		BIT(2)
69 
70 #define FCS_AES_MAX_DATA_SIZE			0x10000000	/* 256 MB */
71 #define FCS_AES_MIN_DATA_SIZE			0x20		/* 32 Byte */
72 #define FCS_AES_CMD_MAX_WORD_SIZE		15U
73 
74 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE	7U
75 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE	19U
76 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE	23U
77 #define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE	4U
78 #define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET	8U
79 /* FCS Payload Structure */
80 typedef struct fcs_rng_payload_t {
81 	uint32_t session_id;
82 	uint32_t context_id;
83 	uint32_t crypto_header;
84 	uint32_t size;
85 } fcs_rng_payload;
86 
87 typedef struct fcs_encrypt_payload_t {
88 	uint32_t first_word;
89 	uint32_t src_addr;
90 	uint32_t src_size;
91 	uint32_t dst_addr;
92 	uint32_t dst_size;
93 } fcs_encrypt_payload;
94 
95 typedef struct fcs_decrypt_payload_t {
96 	uint32_t first_word;
97 	uint32_t owner_id[2];
98 	uint32_t src_addr;
99 	uint32_t src_size;
100 	uint32_t dst_addr;
101 	uint32_t dst_size;
102 } fcs_decrypt_payload;
103 
104 typedef struct fcs_encrypt_ext_payload_t {
105 	uint32_t session_id;
106 	uint32_t context_id;
107 	uint32_t crypto_header;
108 	uint32_t src_addr;
109 	uint32_t src_size;
110 	uint32_t dst_addr;
111 	uint32_t dst_size;
112 } fcs_encrypt_ext_payload;
113 
114 typedef struct fcs_decrypt_ext_payload_t {
115 	uint32_t session_id;
116 	uint32_t context_id;
117 	uint32_t crypto_header;
118 	uint32_t owner_id[2];
119 	uint32_t src_addr;
120 	uint32_t src_size;
121 	uint32_t dst_addr;
122 	uint32_t dst_size;
123 } fcs_decrypt_ext_payload;
124 
125 typedef struct psgsigma_teardown_msg_t {
126 	uint32_t reserved_word;
127 	uint32_t magic_word;
128 	uint32_t session_id;
129 } psgsigma_teardown_msg;
130 
131 typedef struct fcs_cntr_set_preauth_payload_t {
132 	uint32_t first_word;
133 	uint32_t counter_value;
134 } fcs_cntr_set_preauth_payload;
135 
136 typedef struct fcs_cs_key_payload_t {
137 	uint32_t session_id;
138 	uint32_t reserved0;
139 	uint32_t reserved1;
140 	uint32_t key_id;
141 } fcs_cs_key_payload;
142 
143 typedef struct fcs_crypto_service_data_t {
144 	uint32_t session_id;
145 	uint32_t context_id;
146 	uint32_t key_id;
147 	uint32_t crypto_param_size;
148 	uint64_t crypto_param;
149 } fcs_crypto_service_data;
150 
151 typedef struct fcs_crypto_service_aes_data_t {
152 	uint32_t session_id;
153 	uint32_t context_id;
154 	uint32_t param_size;
155 	uint32_t key_id;
156 	uint32_t crypto_param[7];
157 } fcs_crypto_service_aes_data;
158 
159 /* Functions Definitions */
160 
161 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
162 				uint32_t *mbox_error);
163 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id,
164 				uint32_t size, uint32_t *send_id);
165 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
166 				uint32_t *send_id);
167 uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
168 uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type,
169 				int32_t counter_value,
170 				uint32_t test_bit,
171 				uint32_t *mbox_error);
172 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size,
173 				uint32_t dst_addr, uint32_t dst_size,
174 				uint32_t *send_id);
175 
176 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size,
177 				uint32_t dst_addr, uint32_t dst_size,
178 				uint32_t *send_id);
179 
180 int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
181 				uint32_t src_addr, uint32_t src_size,
182 				uint32_t dst_addr, uint32_t *dst_size,
183 				uint32_t *mbox_error);
184 int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id,
185 				uint32_t src_addr, uint32_t src_size,
186 				uint32_t dst_addr, uint32_t *dst_size,
187 				uint32_t *mbox_error);
188 
189 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error);
190 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error);
191 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size,
192 				uint64_t dst_addr, uint32_t *dst_size,
193 				uint32_t *mbox_error);
194 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size,
195 				uint64_t dst_addr, uint32_t *dst_size,
196 				uint32_t *mbox_error);
197 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
198 				uint32_t *mbox_error);
199 
200 int intel_fcs_create_cert_on_reload(uint32_t cert_request,
201 				uint32_t *mbox_error);
202 int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
203 				uint32_t *dst_size, uint32_t *mbox_error);
204 
205 int intel_fcs_open_crypto_service_session(uint32_t *session_id,
206 				uint32_t *mbox_error);
207 int intel_fcs_close_crypto_service_session(uint32_t session_id,
208 				uint32_t *mbox_error);
209 
210 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size,
211 				uint32_t *mbox_error);
212 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id,
213 				uint64_t dst_addr, uint32_t *dst_size,
214 				uint32_t *mbox_error);
215 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id,
216 				uint32_t *mbox_error);
217 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id,
218 				uint64_t dst_addr, uint32_t *dst_size,
219 				uint32_t *mbox_error);
220 
221 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id,
222 				uint32_t key_id, uint32_t param_size,
223 				uint64_t param_data, uint32_t *mbox_error);
224 int intel_fcs_get_digest_finalize(uint32_t session_id, uint32_t context_id,
225 				uint32_t src_addr, uint32_t src_size,
226 				uint64_t dst_addr, uint32_t *dst_size,
227 				uint32_t *mbox_error);
228 
229 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
230 				uint32_t key_id, uint32_t param_size,
231 				uint64_t param_data, uint32_t *mbox_error);
232 int intel_fcs_mac_verify_finalize(uint32_t session_id, uint32_t context_id,
233 				uint32_t src_addr, uint32_t src_size,
234 				uint64_t dst_addr, uint32_t *dst_size,
235 				uint32_t data_size, uint32_t *mbox_error);
236 
237 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id,
238 				uint32_t key_id, uint64_t param_addr,
239 				uint32_t param_size, uint32_t *mbox_error);
240 int intel_fcs_aes_crypt_finalize(uint32_t session_id, uint32_t context_id,
241 				uint64_t src_addr, uint32_t src_size,
242 				uint64_t dst_addr, uint32_t dst_size,
243 				uint32_t *send_id);
244 
245 #endif /* SOCFPGA_FCS_H */
246