1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_SIP_SVC_H 8 #define SOCFPGA_SIP_SVC_H 9 10 11 /* SiP status response */ 12 #define INTEL_SIP_SMC_STATUS_OK 0 13 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 14 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 15 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 16 #define INTEL_SIP_SMC_RSU_ERROR 0x7 17 18 /* SiP mailbox error code */ 19 #define GENERIC_RESPONSE_ERROR 0x3FF 20 21 /* SMC SiP service function identifier */ 22 23 /* FPGA Reconfig */ 24 #define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 25 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 26 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 27 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 28 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 29 30 /* FPGA Bitstream Flag */ 31 #define FLAG_PARTIAL_CONFIG BIT(0) 32 #define FLAG_AUTHENTICATION BIT(1) 33 #define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \ 34 == FLAG_##_type) 35 36 /* Secure Register Access */ 37 #define INTEL_SIP_SMC_REG_READ 0xC2000007 38 #define INTEL_SIP_SMC_REG_WRITE 0xC2000008 39 #define INTEL_SIP_SMC_REG_UPDATE 0xC2000009 40 41 /* Remote System Update */ 42 #define INTEL_SIP_SMC_RSU_STATUS 0xC200000B 43 #define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C 44 #define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E 45 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F 46 #define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010 47 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 48 #define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 49 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 50 #define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 51 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 52 53 /* Hardware monitor */ 54 #define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020 55 #define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021 56 #define TEMP_CHANNEL_MAX (1 << 15) 57 #define VOLT_CHANNEL_MAX (1 << 15) 58 59 /* ECC */ 60 #define INTEL_SIP_SMC_ECC_DBE 0xC200000D 61 62 /* Generic Command */ 63 #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 64 #define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040 65 66 /* Send Mailbox Command */ 67 #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E 68 #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F 69 #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 70 71 /* Mailbox Command */ 72 #define INTEL_SIP_SMC_GET_USERCODE 0xC200003D 73 74 /* FPGA Crypto Services */ 75 #define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B 76 77 /* ECC DBE */ 78 #define WARM_RESET_WFI_FLAG BIT(31) 79 #define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ 80 SYSMGR_ECC_DDR0_MASK |\ 81 SYSMGR_ECC_DDR1_MASK) 82 83 /* Non-mailbox SMC Call */ 84 #define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 85 86 /* SMC function IDs for SiP Service queries */ 87 #define SIP_SVC_CALL_COUNT 0x8200ff00 88 #define SIP_SVC_UID 0x8200ff01 89 #define SIP_SVC_VERSION 0x8200ff03 90 91 /* SiP Service Calls version numbers */ 92 #define SIP_SVC_VERSION_MAJOR 1 93 #define SIP_SVC_VERSION_MINOR 0 94 95 96 /* Structure Definitions */ 97 struct fpga_config_info { 98 uint32_t addr; 99 int size; 100 int size_written; 101 uint32_t write_requested; 102 int subblocks_sent; 103 int block_number; 104 }; 105 106 /* Function Definitions */ 107 bool is_size_4_bytes_aligned(uint32_t size); 108 bool is_address_in_ddr_range(uint64_t addr, uint64_t size); 109 110 /* ECC DBE */ 111 bool cold_reset_for_ecc_dbe(void); 112 uint32_t intel_ecc_dbe_notification(uint64_t dbe_value); 113 114 /* Miscellaneous HPS services */ 115 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask); 116 117 #endif /* SOCFPGA_SIP_SVC_H */ 118