1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_FCS_H 8 #define SOCFPGA_FCS_H 9 10 /* FCS Definitions */ 11 12 #define FCS_RANDOM_WORD_SIZE 8U 13 #define FCS_PROV_DATA_WORD_SIZE 44U 14 #define FCS_SHA384_WORD_SIZE 12U 15 16 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17 #define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U 18 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 19 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 20 21 #define FCS_RANDOM_EXT_OFFSET 3 22 23 #define FCS_MODE_DECRYPT 0x0 24 #define FCS_MODE_ENCRYPT 0x1 25 #define FCS_ENCRYPTION_DATA_0 0x10100 26 #define FCS_DECRYPTION_DATA_0 0x10102 27 #define FCS_OWNER_ID_OFFSET 0xC 28 29 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 30 #define PSGSIGMA_SESSION_ID_ONE 0x1 31 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 32 33 #define RESERVED_AS_ZERO 0x0 34 /* FCS Single cert */ 35 36 #define FCS_BIG_CNTR_SEL 0x1 37 38 #define FCS_SVN_CNTR_0_SEL 0x2 39 #define FCS_SVN_CNTR_1_SEL 0x3 40 #define FCS_SVN_CNTR_2_SEL 0x4 41 #define FCS_SVN_CNTR_3_SEL 0x5 42 43 #define FCS_BIG_CNTR_VAL_MAX 495U 44 #define FCS_SVN_CNTR_VAL_MAX 64U 45 46 /* FCS Attestation Cert Request Parameter */ 47 48 #define FCS_ALIAS_CERT 0x01 49 #define FCS_DEV_ID_SELF_SIGN_CERT 0x02 50 #define FCS_DEV_ID_ENROLL_CERT 0x04 51 #define FCS_ENROLL_SELF_SIGN_CERT 0x08 52 #define FCS_PLAT_KEY_CERT 0x10 53 54 /* FCS Crypto Service */ 55 56 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U 57 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U 58 #define FCS_CS_KEY_RESP_STATUS_MASK 0xFF 59 #define FCS_CS_KEY_RESP_STATUS_OFFSET 16U 60 61 #define FCS_CS_FIELD_SIZE_MASK 0xFFFF 62 #define FCS_CS_FIELD_FLAG_OFFSET 24 63 #define FCS_CS_FIELD_FLAG_INIT BIT(0) 64 #define FCS_CS_FIELD_FLAG_UPDATE BIT(1) 65 #define FCS_CS_FIELD_FLAG_FINALIZE BIT(2) 66 67 /* FCS Payload Structure */ 68 typedef struct fcs_rng_payload_t { 69 uint32_t session_id; 70 uint32_t context_id; 71 uint32_t crypto_header; 72 uint32_t size; 73 } fcs_rng_payload; 74 75 typedef struct fcs_encrypt_payload_t { 76 uint32_t first_word; 77 uint32_t src_addr; 78 uint32_t src_size; 79 uint32_t dst_addr; 80 uint32_t dst_size; 81 } fcs_encrypt_payload; 82 83 typedef struct fcs_decrypt_payload_t { 84 uint32_t first_word; 85 uint32_t owner_id[2]; 86 uint32_t src_addr; 87 uint32_t src_size; 88 uint32_t dst_addr; 89 uint32_t dst_size; 90 } fcs_decrypt_payload; 91 92 typedef struct psgsigma_teardown_msg_t { 93 uint32_t reserved_word; 94 uint32_t magic_word; 95 uint32_t session_id; 96 } psgsigma_teardown_msg; 97 98 typedef struct fcs_cntr_set_preauth_payload_t { 99 uint32_t first_word; 100 uint32_t counter_value; 101 } fcs_cntr_set_preauth_payload; 102 103 typedef struct fcs_cs_key_payload_t { 104 uint32_t session_id; 105 uint32_t reserved0; 106 uint32_t reserved1; 107 uint32_t key_id; 108 } fcs_cs_key_payload; 109 110 /* Functions Definitions */ 111 112 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 113 uint32_t *mbox_error); 114 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id, 115 uint32_t size, uint32_t *send_id); 116 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 117 uint32_t *send_id); 118 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 119 uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, 120 int32_t counter_value, 121 uint32_t test_bit, 122 uint32_t *mbox_error); 123 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 124 uint32_t dst_addr, uint32_t dst_size, 125 uint32_t *send_id); 126 127 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 128 uint32_t dst_addr, uint32_t dst_size, 129 uint32_t *send_id); 130 131 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 132 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 133 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 134 uint64_t dst_addr, uint32_t *dst_size, 135 uint32_t *mbox_error); 136 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 137 uint64_t dst_addr, uint32_t *dst_size, 138 uint32_t *mbox_error); 139 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 140 uint32_t *mbox_error); 141 142 int intel_fcs_create_cert_on_reload(uint32_t cert_request, 143 uint32_t *mbox_error); 144 int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr, 145 uint32_t *dst_size, uint32_t *mbox_error); 146 147 int intel_fcs_open_crypto_service_session(uint32_t *session_id, 148 uint32_t *mbox_error); 149 int intel_fcs_close_crypto_service_session(uint32_t session_id, 150 uint32_t *mbox_error); 151 152 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size, 153 uint32_t *mbox_error); 154 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id, 155 uint64_t dst_addr, uint32_t *dst_size, 156 uint32_t *mbox_error); 157 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id, 158 uint32_t *mbox_error); 159 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id, 160 uint64_t dst_addr, uint32_t *dst_size, 161 uint32_t *mbox_error); 162 163 #endif /* SOCFPGA_FCS_H */ 164