1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_MBOX_H 8 #define SOCFPGA_MBOX_H 9 10 #include <lib/utils_def.h> 11 12 13 #define MBOX_OFFSET 0xffa30000 14 15 #define MBOX_ATF_CLIENT_ID 0x1U 16 #define MBOX_MAX_JOB_ID 0xFU 17 #define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U) 18 #define MBOX_JOB_ID MBOX_MAX_JOB_ID 19 #define MBOX_TEST_BIT BIT(31) 20 21 /* Mailbox Shared Memory Register Map */ 22 #define MBOX_CIN 0x00 23 #define MBOX_ROUT 0x04 24 #define MBOX_URG 0x08 25 #define MBOX_INT 0x0C 26 #define MBOX_COUT 0x20 27 #define MBOX_RIN 0x24 28 #define MBOX_STATUS 0x2C 29 #define MBOX_CMD_BUFFER 0x40 30 #define MBOX_RESP_BUFFER 0xC0 31 32 /* Mailbox SDM doorbell */ 33 #define MBOX_DOORBELL_TO_SDM 0x400 34 #define MBOX_DOORBELL_FROM_SDM 0x480 35 36 37 /* Mailbox commands */ 38 39 #define MBOX_CMD_NOOP 0x00 40 #define MBOX_CMD_SYNC 0x01 41 #define MBOX_CMD_RESTART 0x02 42 #define MBOX_CMD_CANCEL 0x03 43 #define MBOX_CMD_VAB_SRC_CERT 0x0B 44 #define MBOX_CMD_GET_IDCODE 0x10 45 #define MBOX_CMD_GET_USERCODE 0x13 46 #define MBOX_CMD_GET_CHIPID 0x12 47 #define MBOX_CMD_REBOOT_HPS 0x47 48 49 /* Reconfiguration Commands */ 50 #define MBOX_CONFIG_STATUS 0x04 51 #define MBOX_RECONFIG 0x06 52 #define MBOX_RECONFIG_DATA 0x08 53 #define MBOX_RECONFIG_STATUS 0x09 54 55 /* HWMON Commands */ 56 #define MBOX_HWMON_READVOLT 0x18 57 #define MBOX_HWMON_READTEMP 0x19 58 59 60 /* QSPI Commands */ 61 #define MBOX_CMD_QSPI_OPEN 0x32 62 #define MBOX_CMD_QSPI_CLOSE 0x33 63 #define MBOX_CMD_QSPI_SET_CS 0x34 64 #define MBOX_CMD_QSPI_DIRECT 0x3B 65 66 /* RSU Commands */ 67 #define MBOX_GET_SUBPARTITION_TABLE 0x5A 68 #define MBOX_RSU_STATUS 0x5B 69 #define MBOX_RSU_UPDATE 0x5C 70 #define MBOX_HPS_STAGE_NOTIFY 0x5D 71 72 /* FCS Command */ 73 #define MBOX_FCS_GET_PROVISION 0x7B 74 #define MBOX_FCS_CNTR_SET_PREAUTH 0x7C 75 #define MBOX_FCS_ENCRYPT_REQ 0x7E 76 #define MBOX_FCS_DECRYPT_REQ 0x7F 77 #define MBOX_FCS_RANDOM_GEN 0x80 78 #define MBOX_FCS_GET_DIGEST_REQ 0x82 79 #define MBOX_FCS_MAC_VERIFY_REQ 0x83 80 #define MBOX_FCS_OPEN_CS_SESSION 0xA0 81 #define MBOX_FCS_CLOSE_CS_SESSION 0xA1 82 #define MBOX_FCS_IMPORT_CS_KEY 0xA5 83 #define MBOX_FCS_EXPORT_CS_KEY 0xA6 84 #define MBOX_FCS_REMOVE_CS_KEY 0xA7 85 #define MBOX_FCS_GET_CS_KEY_INFO 0xA8 86 87 /* PSG SIGMA Commands */ 88 #define MBOX_PSG_SIGMA_TEARDOWN 0xD5 89 90 /* Attestation Commands */ 91 #define MBOX_CREATE_CERT_ON_RELOAD 0x180 92 #define MBOX_GET_ATTESTATION_CERT 0x181 93 #define MBOX_ATTESTATION_SUBKEY 0x182 94 #define MBOX_GET_MEASUREMENT 0x183 95 96 /* Miscellaneous commands */ 97 #define MBOX_GET_ROM_PATCH_SHA384 0x1B0 98 99 /* Mailbox Definitions */ 100 101 #define CMD_DIRECT 0 102 #define CMD_INDIRECT 1 103 #define CMD_CASUAL 0 104 #define CMD_URGENT 1 105 106 #define MBOX_WORD_BYTE 4U 107 #define MBOX_RESP_BUFFER_SIZE 16 108 #define MBOX_CMD_BUFFER_SIZE 32 109 110 /* Execution states for HPS_STAGE_NOTIFY */ 111 #define HPS_EXECUTION_STATE_FSBL 0 112 #define HPS_EXECUTION_STATE_SSBL 1 113 #define HPS_EXECUTION_STATE_OS 2 114 115 /* Status Response */ 116 #define MBOX_RET_OK 0 117 #define MBOX_RET_ERROR -1 118 #define MBOX_NO_RESPONSE -2 119 #define MBOX_WRONG_ID -3 120 #define MBOX_BUFFER_FULL -4 121 #define MBOX_BUSY -5 122 #define MBOX_TIMEOUT -2047 123 124 /* Reconfig Status Response */ 125 #define RECONFIG_STATUS_STATE 0 126 #define RECONFIG_STATUS_PIN_STATUS 2 127 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 128 #define PIN_STATUS_NSTATUS (U(1) << 31) 129 #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) 130 #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) 131 #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) 132 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 133 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 134 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 135 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 136 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 137 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 138 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 139 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 140 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 141 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 142 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 143 144 145 /* Mailbox Macros */ 146 147 #define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \ 148 + MBOX_WORD_BYTE * (ptr)) 149 150 /* Mailbox interrupt flags and masks */ 151 #define MBOX_INT_FLAG_COE 0x1 152 #define MBOX_INT_FLAG_RIE 0x2 153 #define MBOX_INT_FLAG_UAE 0x100 154 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) 155 #define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) 156 157 /* Mailbox response and status */ 158 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x000007ff) 159 #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) 160 #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) 161 #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) 162 #define MBOX_STATUS_UA_MASK (1<<8) 163 164 /* Mailbox command and response */ 165 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) 166 #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) 167 #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) 168 #define MBOX_INDIRECT(val) ((val) << 11) 169 #define MBOX_CMD_MASK(header) ((header) & 0x7ff) 170 171 /* Mailbox payload */ 172 #define MBOX_DATA_MAX_LEN 0x3ff 173 #define MBOX_PAYLOAD_FLAG_BUSY BIT(0) 174 175 /* RSU Macros */ 176 #define RSU_VERSION_ACMF BIT(8) 177 #define RSU_VERSION_ACMF_MASK 0xff00 178 179 /* Config Status Macros */ 180 #define CONFIG_STATUS_WORD_SIZE 16U 181 #define CONFIG_STATUS_FW_VER_OFFSET 1 182 #define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF 183 184 /* Data structure */ 185 186 typedef struct mailbox_payload { 187 uint32_t header; 188 uint32_t data[MBOX_DATA_MAX_LEN]; 189 } mailbox_payload_t; 190 191 typedef struct mailbox_container { 192 uint32_t flag; 193 uint32_t index; 194 mailbox_payload_t *payload; 195 } mailbox_container_t; 196 197 /* Mailbox Function Definitions */ 198 199 void mailbox_set_int(uint32_t interrupt_input); 200 int mailbox_init(void); 201 void mailbox_set_qspi_close(void); 202 void mailbox_hps_qspi_enable(void); 203 204 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, 205 unsigned int len, uint32_t urgent, uint32_t *response, 206 unsigned int *resp_len); 207 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, 208 unsigned int len, unsigned int indirect); 209 int mailbox_read_response(uint32_t *job_id, uint32_t *response, 210 unsigned int *resp_len); 211 int mailbox_read_response_async(uint32_t *job_id, uint32_t *header, 212 uint32_t *response, unsigned int *resp_len, 213 uint8_t ignore_client_id); 214 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, 215 unsigned int *resp_len); 216 217 void mailbox_reset_cold(void); 218 void mailbox_clear_response(void); 219 220 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done); 221 int intel_mailbox_is_fpga_not_ready(void); 222 223 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); 224 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); 225 int mailbox_rsu_update(uint32_t *flash_offset); 226 int mailbox_hps_stage_notify(uint32_t execution_stage); 227 int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf); 228 int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf); 229 230 #endif /* SOCFPGA_MBOX_H */ 231