1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_FCS_H 8 #define SOCFPGA_FCS_H 9 10 /* FCS Definitions */ 11 12 #define FCS_RANDOM_WORD_SIZE 8U 13 #define FCS_PROV_DATA_WORD_SIZE 44U 14 #define FCS_SHA384_WORD_SIZE 12U 15 16 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 18 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 19 20 #define FCS_MODE_DECRYPT 0x0 21 #define FCS_MODE_ENCRYPT 0x1 22 #define FCS_ENCRYPTION_DATA_0 0x10100 23 #define FCS_DECRYPTION_DATA_0 0x10102 24 #define FCS_OWNER_ID_OFFSET 0xC 25 26 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 27 #define PSGSIGMA_SESSION_ID_ONE 0x1 28 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 29 30 #define RESERVED_AS_ZERO 0x0 31 /* FCS Single cert */ 32 33 #define FCS_BIG_CNTR_SEL 0x1 34 35 #define FCS_SVN_CNTR_0_SEL 0x2 36 #define FCS_SVN_CNTR_1_SEL 0x3 37 #define FCS_SVN_CNTR_2_SEL 0x4 38 #define FCS_SVN_CNTR_3_SEL 0x5 39 40 #define FCS_BIG_CNTR_VAL_MAX 495U 41 #define FCS_SVN_CNTR_VAL_MAX 64U 42 43 /* FCS Attestation Cert Request Parameter */ 44 45 #define FCS_ALIAS_CERT 0x01 46 #define FCS_DEV_ID_SELF_SIGN_CERT 0x02 47 #define FCS_DEV_ID_ENROLL_CERT 0x04 48 #define FCS_ENROLL_SELF_SIGN_CERT 0x08 49 #define FCS_PLAT_KEY_CERT 0x10 50 51 /* FCS Crypto Service */ 52 53 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U 54 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U 55 #define FCS_CS_KEY_RESP_STATUS_MASK 0xFF 56 #define FCS_CS_KEY_RESP_STATUS_OFFSET 16U 57 58 /* FCS Payload Structure */ 59 60 typedef struct fcs_encrypt_payload_t { 61 uint32_t first_word; 62 uint32_t src_addr; 63 uint32_t src_size; 64 uint32_t dst_addr; 65 uint32_t dst_size; 66 } fcs_encrypt_payload; 67 68 typedef struct fcs_decrypt_payload_t { 69 uint32_t first_word; 70 uint32_t owner_id[2]; 71 uint32_t src_addr; 72 uint32_t src_size; 73 uint32_t dst_addr; 74 uint32_t dst_size; 75 } fcs_decrypt_payload; 76 77 typedef struct psgsigma_teardown_msg_t { 78 uint32_t reserved_word; 79 uint32_t magic_word; 80 uint32_t session_id; 81 } psgsigma_teardown_msg; 82 83 typedef struct fcs_cntr_set_preauth_payload_t { 84 uint32_t first_word; 85 uint32_t counter_value; 86 } fcs_cntr_set_preauth_payload; 87 88 typedef struct fcs_cs_key_payload_t { 89 uint32_t session_id; 90 uint32_t reserved0; 91 uint32_t reserved1; 92 uint32_t key_id; 93 } fcs_cs_key_payload; 94 95 /* Functions Definitions */ 96 97 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 98 uint32_t *mbox_error); 99 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 100 uint32_t *send_id); 101 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 102 uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, 103 int32_t counter_value, 104 uint32_t test_bit, 105 uint32_t *mbox_error); 106 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 107 uint32_t dst_addr, uint32_t dst_size, 108 uint32_t *send_id); 109 110 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 111 uint32_t dst_addr, uint32_t dst_size, 112 uint32_t *send_id); 113 114 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 115 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 116 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 117 uint64_t dst_addr, uint32_t *dst_size, 118 uint32_t *mbox_error); 119 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 120 uint64_t dst_addr, uint32_t *dst_size, 121 uint32_t *mbox_error); 122 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 123 uint32_t *mbox_error); 124 125 int intel_fcs_create_cert_on_reload(uint32_t cert_request, 126 uint32_t *mbox_error); 127 int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr, 128 uint32_t *dst_size, uint32_t *mbox_error); 129 130 int intel_fcs_open_crypto_service_session(uint32_t *session_id, 131 uint32_t *mbox_error); 132 int intel_fcs_close_crypto_service_session(uint32_t session_id, 133 uint32_t *mbox_error); 134 135 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size, 136 uint32_t *mbox_error); 137 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id, 138 uint64_t dst_addr, uint32_t *dst_size, 139 uint32_t *mbox_error); 140 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id, 141 uint32_t *mbox_error); 142 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id, 143 uint64_t dst_addr, uint32_t *dst_size, 144 uint32_t *mbox_error); 145 146 #endif /* SOCFPGA_FCS_H */ 147