1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_SIP_SVC_H 8 #define SOCFPGA_SIP_SVC_H 9 10 11 /* SiP status response */ 12 #define INTEL_SIP_SMC_STATUS_OK 0 13 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 14 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 15 #define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3 16 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 17 #define INTEL_SIP_SMC_RSU_ERROR 0x7 18 19 /* SiP mailbox error code */ 20 #define GENERIC_RESPONSE_ERROR 0x3FF 21 22 /* SMC SiP service function identifier */ 23 24 /* FPGA Reconfig */ 25 #define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 26 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 27 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 28 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 29 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 30 31 /* FPGA Bitstream Flag */ 32 #define FLAG_PARTIAL_CONFIG BIT(0) 33 #define FLAG_AUTHENTICATION BIT(1) 34 #define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \ 35 == FLAG_##_type) 36 37 /* Secure Register Access */ 38 #define INTEL_SIP_SMC_REG_READ 0xC2000007 39 #define INTEL_SIP_SMC_REG_WRITE 0xC2000008 40 #define INTEL_SIP_SMC_REG_UPDATE 0xC2000009 41 42 /* Remote System Update */ 43 #define INTEL_SIP_SMC_RSU_STATUS 0xC200000B 44 #define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C 45 #define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E 46 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F 47 #define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010 48 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 49 #define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 50 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 51 #define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 52 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 53 54 /* Hardware monitor */ 55 #define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020 56 #define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021 57 #define TEMP_CHANNEL_MAX (1 << 15) 58 #define VOLT_CHANNEL_MAX (1 << 15) 59 60 /* ECC */ 61 #define INTEL_SIP_SMC_ECC_DBE 0xC200000D 62 63 /* Generic Command */ 64 #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 65 #define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040 66 67 /* Send Mailbox Command */ 68 #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E 69 #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F 70 #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 71 72 #define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E 73 74 /* Mailbox Command */ 75 #define INTEL_SIP_SMC_GET_USERCODE 0xC200003D 76 77 /* FPGA Crypto Services */ 78 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A 79 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F 80 #define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B 81 #define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D 82 #define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E 83 #define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F 84 #define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064 85 #define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065 86 #define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066 87 #define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067 88 #define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068 89 #define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069 90 #define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E 91 #define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F 92 #define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070 93 #define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071 94 #define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072 95 #define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073 96 #define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077 97 #define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079 98 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A 99 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C 100 101 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF 102 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF 103 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U 104 /* ECC DBE */ 105 #define WARM_RESET_WFI_FLAG BIT(31) 106 #define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ 107 SYSMGR_ECC_DDR0_MASK |\ 108 SYSMGR_ECC_DDR1_MASK) 109 110 /* Non-mailbox SMC Call */ 111 #define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 112 113 /* SMC function IDs for SiP Service queries */ 114 #define SIP_SVC_CALL_COUNT 0x8200ff00 115 #define SIP_SVC_UID 0x8200ff01 116 #define SIP_SVC_VERSION 0x8200ff03 117 118 /* SiP Service Calls version numbers */ 119 #define SIP_SVC_VERSION_MAJOR 1 120 #define SIP_SVC_VERSION_MINOR 0 121 122 123 /* Structure Definitions */ 124 struct fpga_config_info { 125 uint32_t addr; 126 int size; 127 int size_written; 128 uint32_t write_requested; 129 int subblocks_sent; 130 int block_number; 131 }; 132 133 /* Function Definitions */ 134 bool is_size_4_bytes_aligned(uint32_t size); 135 bool is_address_in_ddr_range(uint64_t addr, uint64_t size); 136 137 /* ECC DBE */ 138 bool cold_reset_for_ecc_dbe(void); 139 uint32_t intel_ecc_dbe_notification(uint64_t dbe_value); 140 141 /* Miscellaneous HPS services */ 142 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask); 143 144 #endif /* SOCFPGA_SIP_SVC_H */ 145