1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_FCS_H 8 #define SOCFPGA_FCS_H 9 10 /* FCS Definitions */ 11 12 #define FCS_RANDOM_WORD_SIZE 8U 13 #define FCS_PROV_DATA_WORD_SIZE 44U 14 #define FCS_SHA384_WORD_SIZE 12U 15 16 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 18 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 19 20 #define FCS_MODE_DECRYPT 0x0 21 #define FCS_MODE_ENCRYPT 0x1 22 #define FCS_ENCRYPTION_DATA_0 0x10100 23 #define FCS_DECRYPTION_DATA_0 0x10102 24 #define FCS_OWNER_ID_OFFSET 0xC 25 26 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 27 #define PSGSIGMA_SESSION_ID_ONE 0x1 28 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 29 30 #define RESERVED_AS_ZERO 0x0 31 32 /* FCS Payload Structure */ 33 34 typedef struct fcs_encrypt_payload_t { 35 uint32_t first_word; 36 uint32_t src_addr; 37 uint32_t src_size; 38 uint32_t dst_addr; 39 uint32_t dst_size; 40 } fcs_encrypt_payload; 41 42 typedef struct fcs_decrypt_payload_t { 43 uint32_t first_word; 44 uint32_t owner_id[2]; 45 uint32_t src_addr; 46 uint32_t src_size; 47 uint32_t dst_addr; 48 uint32_t dst_size; 49 } fcs_decrypt_payload; 50 51 typedef struct psgsigma_teardown_msg_t { 52 uint32_t reserved_word; 53 uint32_t magic_word; 54 uint32_t session_id; 55 } psgsigma_teardown_msg; 56 57 58 /* Functions Definitions */ 59 60 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 61 uint32_t *mbox_error); 62 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 63 uint32_t *send_id); 64 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 65 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 66 uint32_t dst_addr, uint32_t dst_size, 67 uint32_t *send_id); 68 69 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 70 uint32_t dst_addr, uint32_t dst_size, 71 uint32_t *send_id); 72 73 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 74 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 75 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 76 uint64_t dst_addr, uint32_t *dst_size, 77 uint32_t *mbox_error); 78 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 79 uint64_t dst_addr, uint32_t *dst_size, 80 uint32_t *mbox_error); 81 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 82 uint32_t *mbox_error); 83 84 #endif /* SOCFPGA_FCS_H */ 85