Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with o

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with out-of-bounds read
fix(fvp): fix coverity issue unsigned_compare

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Merge "fix(scmi): fix coverity issue INTEGER_OVERFLOW" into integration

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(gic): fix coverity issue INTEGER_OVERFLOW
fix(scmi): fix coverity issue INTEGER_OVERFLOW

fix(build): fix incorrect expansions in `shell-map`

The `shell-map` function needs to pass values it receives from the shell
back into Make for evaluation, which requires certain special characters

fix(build): fix incorrect expansions in `shell-map`

The `shell-map` function needs to pass values it receives from the shell
back into Make for evaluation, which requires certain special characters
to be escaped.

This escaping is currently resulting in those characters *not* being
escaped, and consequently instead generates some funky (unhelpful)
syntax errors half-way through reading the Makefile.

This change corrects the escape substitutions so that they are evaluated
as expected within Make.

Change-Id: I7b47a48342f626efe362e05283ee59520673375f
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register def

Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register defines and read helpers

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Merge "docs(cpufeat): add a checklist on how to add a feature" into integration

Merge "fix(qti): uart platform base address for SC7180" into integration

fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmwa

fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/43574/5/plat/qti/sc7180/inc/platform_def.h

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Change-Id: I4d34db01720ce289a87bccf0338205b4861e11cb

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fix(build): set linker to lld before evaluating ld_option

This ensures ld_option is called with valid -fuse-ld option, therefore
filtering options against ones supported by lld and not the
system de

fix(build): set linker to lld before evaluating ld_option

This ensures ld_option is called with valid -fuse-ld option, therefore
filtering options against ones supported by lld and not the
system default linker Clang chooses without the option specified.

This change should not affect toolchains other than llvm-clang, since it
only moves a conditional concerning the said toolchain.

Resolves the following linking error that manifests itself when using
Clang versions 21 and higher for building TF-A:

> ld.lld: error: unknown argument '--no-warn-rwx-segments'

Change-Id: I466f733377327a7c38ee27899be6681debf61e11
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>

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feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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feat(cpufeat): include enabled security state scope

This patch adds a security state scope to feature function creation.
The scope defines the set of worlds (Secure, Non-secure, and Realm)
for which

feat(cpufeat): include enabled security state scope

This patch adds a security state scope to feature function creation.
The scope defines the set of worlds (Secure, Non-secure, and Realm)
for which a given feature is enabled. This allows finer-grained
control of feature visibility and ensures that ID register are
updated based on feature's enablement status for that world.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia4ba4ea7c0b020a398785a28e7ce25b00ab1f4ec

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feat(cpufeat): add ID register defines and read helpers

Add system register encodings and read helper functions for
both AArch32 and AArch64 ID registers.

These additions complete the set of archit

feat(cpufeat): add ID register defines and read helpers

Add system register encodings and read helper functions for
both AArch32 and AArch64 ID registers.

These additions complete the set of architectural ID registers that
may be trapped as part of FEAT_IDTE3, which enables EL3 to intercept
ID register accesses from lower exception levels.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5d73b78e80d56a0b78ce026dcf70373c8aabd857

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Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
f

Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2
feat(per-cpu): migrate amu_ctx to per-cpu framework
feat(per-cpu): migrate spm_core_context to per-cpu framework
feat(per-cpu): migrate psci_ns_context to per-cpu framework
feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework
feat(per-cpu): migrate rmm_context to per-cpu framework
feat(per-cpu): integrate per-cpu framework into BL31/BL32
feat(per-cpu): introduce framework accessors/definers
feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework
docs(changelog): add scope for per-cpu framework

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Merge "fix(rmm): enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM" into integration

Merge changes from topic "ar/pre-idte3" into integration

* changes:
feat(el3-runtime): add flags argument to handle_sysreg_trap
fix(cpufeat): remove unused FEAT_NV feature functions

docs(maintainers): add per-cpu framework into maintainers.rst

Add Rohit Mathew <rohit.mathew@arm.com> and Sammit Joshi
<sammit.joshi@arm.com> as code owners for the per-CPU framework.

Add Manish Pa

docs(maintainers): add per-cpu framework into maintainers.rst

Add Rohit Mathew <rohit.mathew@arm.com> and Sammit Joshi
<sammit.joshi@arm.com> as code owners for the per-CPU framework.

Add Manish Pandey <manish.pandey2@arm.com> and
Chris Kay <chris.kay@arm.com> as a code owner alongside
the authors.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: If81e097d8b52d083cff9e0722c5550322cffd245

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feat(per-cpu): add documentation for per-cpu framework

add documentation for numa aware per-cpu framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Sammit Joshi <sammit.jos

feat(per-cpu): add documentation for per-cpu framework

add documentation for numa aware per-cpu framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ibd39adea95aa24abb588ff518547bdc1ec46b0fe

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feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cp

feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cpu objects within a memory that is local to a particular node.
RD-V3-Cfg2 in this case has the per-cpu objects distributed across
different SRAMs present on the system.

introduce platform-specific helper functions to enhance the per_cpu
framework. Adds a helper function to zero init per_cpu sections,
ensuring clean initialization of per-cpu data. Introduces a function
to obtain the base address of per_cpu sections, facilitating efficient
access to per-CPU data structures. Enhances the per_cpu framework's
capability to handle platform-specific requirements.

These additions are crucial for maintaining the integrity and
performance of per-cpu operations.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I550c6b5c59f80fbe2b746a1261cda857f4fb1990

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feat(per-cpu): migrate amu_ctx to per-cpu framework

migrate amu_ctx object to the NUMA-aware per-cpu framework
to optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Jos

feat(per-cpu): migrate amu_ctx to per-cpu framework

migrate amu_ctx object to the NUMA-aware per-cpu framework
to optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I55e5e923ddd7307039e0cd9a35e91d908f910d10

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feat(per-cpu): migrate spm_core_context to per-cpu framework

migrate spm_core_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed

feat(per-cpu): migrate spm_core_context to per-cpu framework

migrate spm_core_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie600ae755cfb738adde51cfc4af3cddbbccbbaef

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feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-of

feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ie8b9f4eea8c61d4de9996d9370634cbd08ff1d8d

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feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signe

feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idec3e3b74ecf03b420b339a183be2b9e00f8a78f

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feat(per-cpu): migrate rmm_context to per-cpu framework

migrate rmm_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: S

feat(per-cpu): migrate rmm_context to per-cpu framework

migrate rmm_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I72d49c3d860dac10bd3930ce400b0199bedd887b

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feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clear

feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clears them
during early C runtime initialization. For platforms that enable
NUMA_AWARE_PER_CPU, invokes a platform hook to zero-initialize
node-specific per-cpu regions.

Cache maintenance: Extends the BL31 exit path to clean dcache lines
covering the per-cpu region, ensuring data written by the primary core
is visible to secondary cores.

tpidr_el3 setup: Initializes tpidr_el3 with the base address of the
current CPU’s per-cpu section. This allows per-cpu framework to
resolve local cpu accesses efficiently.

The percpu_data object is currently stored in tpidr_el3. Since the
per-cpu framework will use tpidr_el3 for this-cpu access, percpu_data
must be migrated to avoid conflict. This commit moves percpu_data to
the per-cpu framework.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iff0c2e1f8c0ebd25c4bb0b09bfe15dd4fbe20561

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feat(per-cpu): introduce framework accessors/definers

Introduce per-cpu framework definers and accessors for allocation and
access of per-cpu objects. The accessors support "per_cpu_cur" variants
fo

feat(per-cpu): introduce framework accessors/definers

Introduce per-cpu framework definers and accessors for allocation and
access of per-cpu objects. The accessors support "per_cpu_cur" variants
for access on the calling CPU as well as "per_cpu_by_index" variants for
access on any CPU. Additionally, the framework supports NUMA-aware
allocation, allowing the per-cpu data to be distributed across different
memory nodes. This enables the system to allocate per-cpu data on memory
nodes closest to the respective CPU, optimising memory access and
performance.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8361602ff626dcfe9405e7e2a28c5d143aaac574

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