fix(cpus): workaround for Cortex-X925 erratum 3692980

Cortex-X925 erratum 3692980 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

This erratum can be avoided by set

fix(cpus): workaround for Cortex-X925 erratum 3692980

Cortex-X925 erratum 3692980 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR6_EL1[41] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: If2b88e3a23bda424ba17ab5cead07e7d701db2e3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-X925 erratum 3324334

Cortex-X925 erratum 3324334 is a Cat B erratum that
applies to revisions r0p0, r0p1 and is fixed in r0p2.

This erratum can be avoided by adding

fix(cpus): workaround for Cortex-X925 erratum 3324334

Cortex-X925 erratum 3324334 is a Cat B erratum that
applies to revisions r0p0, r0p1 and is fixed in r0p2.

This erratum can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I57d2b306b0a3128f3786f4797e6765234ad429cf
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-X925 erratum 2933290

Cortex-X925 erratum 2933290 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

MTE Tag checking may not be performed if an access th

fix(cpus): workaround for Cortex-X925 erratum 2933290

Cortex-X925 erratum 2933290 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

MTE Tag checking may not be performed if an access that crosses
a 16-byte boundary encounters a poisoned Allocation tag. This
erratum can be avoided by setting CPUACTLR5_EL1[42] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I6d5c680a3d5156b3b17d59de79f8b650d56deff3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-X925 erratum 2922378

Cortex-X925 erratum 2922378 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Branch prediction history is not suppressed when swit

fix(cpus): workaround for Cortex-X925 erratum 2922378

Cortex-X925 erratum 2922378 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Branch prediction history is not suppressed when switching from low
to high EL, this erratum can be avoided by setting the CPUACTLR4[10]
to 1 and CPUACTLR4[11] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: Ieb5fe278821d85382af60be25e9546e65ba9a629
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge "feat(mt8196): add booker driver" into integration

Merge "feat(lib): add mmio_setbits_64 inline function" into integration

fix(cpus): workaround for Cortex-X925 erratum 2921199

Cortex-X925 erratum 2921199 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Under certain rare microarchitectural conditions, two

fix(cpus): workaround for Cortex-X925 erratum 2921199

Cortex-X925 erratum 2921199 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Under certain rare microarchitectural conditions, two or more STG
instructions that access the same cache line but different 32-bytes
might not write the MTE allocation tag to memory. This erratum can
be avoided by setting CPUACTLR5_EL1[14] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I8eb8bbdd6f99f69c8713400191ac66f55ffedc8b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

feat(mt8196): add booker driver

The booker tag cache will be lost when mcusys off, so it needs to be
flushed to DRAM during the power-off sequence.

Signed-off-by: Runyang Chen <runyang.chen@mediate

feat(mt8196): add booker driver

The booker tag cache will be lost when mcusys off, so it needs to be
flushed to DRAM during the power-off sequence.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Change-Id: I71ddd1f9d1613ce4f5bc10103683b504573e2842

show more ...

feat(lib): add mmio_setbits_64 inline function

Add mmio 64 bits set utility function.

Change-Id: I35c54d1c0e981f6a68eb8fd1101947451dcf253f
Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>

Merge changes from topic "xl/c1nano-errata" into integration

* changes:
fix(cpus): workaround for C1-Nano erratum 3754876
fix(cpus): workaround for C1-Nano erratum 3419531
fix(cpus): workaroun

Merge changes from topic "xl/c1nano-errata" into integration

* changes:
fix(cpus): workaround for C1-Nano erratum 3754876
fix(cpus): workaround for C1-Nano erratum 3419531
fix(cpus): workaround for C1-Nano erratum 3630925
fix(cpus): workaround for C1-Nano erratum 3616450
fix(cpus): workaround for C1-Nano erratum 3516455
fix(cpus): workaround for C1-Nano erratum 3437202
fix(cpus): workaround for C1-Nano erratum 3392149

show more ...

Merge changes from topic "v3_errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3312417
fix(cpus): workaround for Neoverse V3 erratum 3878291
fix(cpus): workarou

Merge changes from topic "v3_errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3312417
fix(cpus): workaround for Neoverse V3 erratum 3878291
fix(cpus): workaround for Neoverse V3 erratum 3864536
fix(cpus): workaround for Neoverse V3 erratum 3782181
fix(cpus): workaround for Neoverse V3 erratum 3734562
fix(cpus): workaround for Neoverse V3 erratum 3696307

show more ...

fix(cpus): workaround for C1-Nano erratum 3754876

C1-Nano erratum 3754876 is a Cat B erratum that applies
to revisions r0p0, and r0p1, and is fixed in r0p2.

This errata can be avoided by executing

fix(cpus): workaround for C1-Nano erratum 3754876

C1-Nano erratum 3754876 is a Cat B erratum that applies
to revisions r0p0, and r0p1, and is fixed in r0p2.

This errata can be avoided by executing a TSB CSYNC
before executing a WFI instruction for power down.
Which prevents core deadlock during power down if
Trace Buffer Extension (TRBE) is enabled.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I3528f08c028b50be848b8d6113d370414261ad48
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Nano erratum 3419531

C1-Nano erratum 3419531 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by setting IMP_CPUACTLR_

fix(cpus): workaround for C1-Nano erratum 3419531

C1-Nano erratum 3419531 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by setting IMP_CPUACTLR_EL1[27] to
1, which disable write streaming for MTE stores when MTE
feature is enabled.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: Ib5103483163a1f93cbb2df8c3b3fcfb2c6d487c6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Nano erratum 3630925

C1-Nano erratum 3630925 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by disable entering full

fix(cpus): workaround for C1-Nano erratum 3630925

C1-Nano erratum 3630925 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by disable entering full
retention mode by setting both IMP_CPUPWRCTLR_EL1[9:7] and
IMP_CPUPWRCTLR_EL1[6:4] to 3'b000.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I61cdf21b50dfb534ce2a1e74c22b06bde9a7c0a7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Nano erratum 3616450

C1-Nano erratum 3616450 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might result in data corruption under
u

fix(cpus): workaround for C1-Nano erratum 3616450

C1-Nano erratum 3616450 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might result in data corruption under
uncommon micro-architectural conditions for SME, SIMD&FP,
or SVE load or store. This can be avoided by setting
IMP_CPUACTLR_EL1[29] to 1. This workaround will reduce
the effectiveness of internal clock gating, and can have
a small impact on power efficiency. During power testing
of sample silicon, Arm recommends not applying the
workaround.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I542be9a051a1f17e93c21bef725f7ede429555f9
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge "chore: bump event log library" into integration

fix(cpus): workaround for C1-Nano erratum 3516455

C1-Nano erratum 3516455 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might cause the core to deadlock in
str

fix(cpus): workaround for C1-Nano erratum 3516455

C1-Nano erratum 3516455 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might cause the core to deadlock in
streaming mode when Non-SME instruction abort.
Which can be avoided by restricts address generation
based on speculatively produced data for vector
load/stores accessing 4 vector registers in streaming SVE
mode. The workaround can have a minor impact on
performance in heavy streaming SVE workloads, depending
on the density of the affected instructions

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: Id97fbfd1d76e9dc1a3488ce33e353c032c41e0f1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Nano erratum 3437202

C1-Nano erratum 3437202 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might might lead to data corruption, wh

fix(cpus): workaround for C1-Nano erratum 3437202

C1-Nano erratum 3437202 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might might lead to data corruption, which
can be avoided by seting IMP_CPUACTLR_EL1[26] to 1.
The workaround is expected to have negligible performance
and power impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: If6c12a7a26ccd67496909481a9683151d30d4339
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Nano erratum 3392149

C1-Nano erratum 3392149 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might cause deadlock when receiving an

fix(cpus): workaround for C1-Nano erratum 3392149

C1-Nano erratum 3392149 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might cause deadlock when receiving an I-cache
invalidation, which can be avoided by seting
IMP_CPUACTLR3_EL1[39] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I530c75acf25ee57efaf7ff58ef4a43508fb6d52a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

chore: bump event log library

This fixes bugs in the library.

Change-Id: Ib35b22ac5998b71b4049077bf34f92a0cd6d866d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

feat(locks): make spin_trylock with exclusives spin until it knows the state of the lock

spin_trylock() is meant to be a non-blocking equivalent of spin_lock().
When we have atomics this is easy - t

feat(locks): make spin_trylock with exclusives spin until it knows the state of the lock

spin_trylock() is meant to be a non-blocking equivalent of spin_lock().
When we have atomics this is easy - the `cas` will directly return the
state of the lock (held or not held). However, when using exclusives,
there's a third state - failed to hold the lock. This happens when the
store exclusive couldn't complete the write and bailed. The current
implementation will pigeonhole this state into a "not held" state which
loses this subtlety and can return with no one holding the lock.

This patch makes it so that the operation is retried until the core is
certain it either holds the lock or someone else does. This keeps the
nonblocking nature of the trylock call but may incur a delay until the
state of the lock settles.

Change-Id: I1a57de22557e13c22f6a6afdef4c28f679dbe7f2
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(locks): restore spin_trylock's ability to acquire a lock

The FEAT_STATE conversion of spinlocks (patch
38e580e6411c7a2eb2801a6aacb0a19bb9b1ac46) missed a branch between the
two `mov` instruction

fix(locks): restore spin_trylock's ability to acquire a lock

The FEAT_STATE conversion of spinlocks (patch
38e580e6411c7a2eb2801a6aacb0a19bb9b1ac46) missed a branch between the
two `mov` instructions and as a result the `mov rx, #1` is always
followed by `mov rx, #0` causing the spin_trylock() function to always
return failure.

Putting the branch back into the inline assembly is difficult without
extra C control logic that would add extra instructions. So instead
keep only the exclusives in assembly and convert all control logic to C.
This emits code that is functionally equivalent to the original with the
same number of instructions.

Change-Id: If97ea5fd46321ec18c8f92368355b1bc004a7cf0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge "fix(tc): configure mte addresses and sizes" into integration

fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout

fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout is not included when building FVP.
FVP's do not require a physical carveout to
emulate MTE, so we can save the memory.
- Add memory map diagrams to platform_def.h
- Tidy up existing memory map macros.

Change-Id: I4d31aa27e470344d4ed6469939331d0e2ced9d54
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

fix(rdaspen): dts: make cache nodes DT spec compliant

The Devicetree specification demands that L2 and L3 cache nodes using
the unified property names (cache-size instead of
i-cache-size/d-cache-siz

fix(rdaspen): dts: make cache nodes DT spec compliant

The Devicetree specification demands that L2 and L3 cache nodes using
the unified property names (cache-size instead of
i-cache-size/d-cache-size), are required to carry a "cache-unified"
boolean property. Also the node names must be just "l2-cache" or
"l3-cache", without any further numbering. Finally there should be no
specific compatible string for the L3 cache, just "cache" is enough.

Fix the cache description in the RDAspen devicetree to make it pass
the Linux kernel DTB checks.

Change-Id: If634c8e841ceb5c83079738d82fcdb9c13d327ad
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...