refactor(mediatek): move ptp3_plat.h to common code

To improve code reusability, move the common code from
mt8188/ptp3_plat.h and mt8195/ptp3_plat.h into ptp3_common.h. Place the
platform-specific c

refactor(mediatek): move ptp3_plat.h to common code

To improve code reusability, move the common code from
mt8188/ptp3_plat.h and mt8195/ptp3_plat.h into ptp3_common.h. Place the
platform-specific code in ptp3_plat_v1.h for mt8195 and ptp3_plat_v2.h
for mt8188.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: I38c32fa3ad03f9dc7a653ed89da335d26f70f75b

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fix(mt8195): fix variable may be used uninitialized error

Change-Id: Ic0e6e286ea764ef26f4f43e327177fb653e15b07
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

refactor(mediatek): move headers to common folder

The plat_macros.S and plat_private.h are identical across some
platforms, moved to the common folder for easier maintenance.

Change-Id: I31c71551aa

refactor(mediatek): move headers to common folder

The plat_macros.S and plat_private.h are identical across some
platforms, moved to the common folder for easier maintenance.

Change-Id: I31c71551aa0e891f080e58f21e6e79551d2a19e0
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(aarch64): add DBGPRCR_EL1 register accessors

This is a small change adding accessor functions for the Debug Power
Control register (DBGPRCR_EL1) to the common architectural helpers.

Change-Id:

feat(aarch64): add DBGPRCR_EL1 register accessors

This is a small change adding accessor functions for the Debug Power
Control register (DBGPRCR_EL1) to the common architectural helpers.

Change-Id: I72261fbf0395d900347b46af320093ed946aa73d
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(mediatek): move plat_helpers.h to the common folder

The plat_helpers.h is identical across various platforms, moved to the
common folder for easier maintenance.

Change-Id: Ic9f10c697fcda7e3cfb

feat(mediatek): move plat_helpers.h to the common folder

The plat_helpers.h is identical across various platforms, moved to the
common folder for easier maintenance.

Change-Id: Ic9f10c697fcda7e3cfbf32e67486c9cd28481b8a
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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feat(mt8195): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/bas

feat(mt8195): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/mtscp-rv32i/baseboard.h;l=149

Change-Id: I7b104c8ea8ee7f13d829a79f0a310d93ea466215
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>

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feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK

feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846

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