Merge pull request #1849 from loumay-arm/lm/a73_errata

Cortex-A73: Implement workaround for errata 852427

Merge pull request #1845 from ambroise-arm/av/errata

Apply workarounds for errata of Cortex-A53, A55 and A57

Merge pull request #1846 from loumay-arm/lm/mpam

MPAM: enable MPAM EL2 traps

Merge pull request #1848 from antonio-nino-diaz-arm/an/docs

Minor changes to documentation and comments

xlat_tables_v2: find VA/idx with helper functions.

This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by

xlat_tables_v2: find VA/idx with helper functions.

This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by the
specified mmap region. it reduces code duplication and cyclomatic code
complexity in xlat_tables_map/unmap_region functions.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>

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xlat_tables_v2: get unmap action type with helper function.

This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmappin

xlat_tables_v2: get unmap action type with helper function.

This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmapping the
specified region.
it reduces cyclomatic code complexity in xlat_tables_unmap_region function.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>

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Minor changes to documentation and comments

Fix some typos and clarify some sentences.

Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.co

Minor changes to documentation and comments

Fix some typos and clarify some sentences.

Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Cortex-A73: Implement workaround for errata 852427

In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of th

Cortex-A73: Implement workaround for errata 852427

In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.

Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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MPAM: enable MPAM EL2 traps

Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2
traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an
MPAM-unaware-hypervisor to be restricted by an

MPAM: enable MPAM EL2 traps

Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2
traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an
MPAM-unaware-hypervisor to be restricted by an MPAM-aware-guest.

Change-Id: I47bf3f833fa22baa590f83d49cc0e3f2974e698d
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Merge pull request #1839 from loumay-arm/lm/a7x_errata

Cortex-A73/75/76 errata workaround

Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0

Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Cortex-A57: Implement workaround for erratum 817169

Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A57: Implement workaround for erratum 814670

Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A55: Implement workaround for erratum 903758

Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A55: Implement workaround for erratum 846532

Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A55: Implement workaround for erratum 798797

Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A55: Implement workaround for erratum 778703

Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A55: Implement workaround for erratum 768277

Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Tegra: Support for scatterfile for the BL31 image

This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable

Tegra: Support for scatterfile for the BL31 image

This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable the scatterfile usage the following changes
have been made:

* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
to compile BL31
* update pubsub.h to add sections to the scatterfile

NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.

Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Add support for pointer authentication

The previous commit added the infrastructure to load and save
ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
didn't actually enable p

Add support for pointer authentication

The previous commit added the infrastructure to load and save
ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
didn't actually enable pointer authentication in the firmware.

This patch adds the functionality needed for platforms to provide
authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
enable pointer authentication in the firmware itself. This option is
disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
enabled.

Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Add ARMv8.3-PAuth registers to CPU context

ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indire

Add ARMv8.3-PAuth registers to CPU context

ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.

This feature is supported only in AArch64 state.

This feature is mandatory in ARMv8.3 implementations.

This feature adds several registers to EL1. A new option called
CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
them during Non-secure <-> Secure world switches. This option must be
enabled if the hardware has the registers or the values will be leaked
during world switches.

To prevent leaks, this patch also disables pointer authentication in the
Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
be trapped in EL3.

Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Cleanup context handling library

Minor style cleanup.

Change-Id: Ief19dece41a989e2e8157859a265701549f6c585
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Add workaround for errata 1073348 for Cortex-A76

Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Add workaround for errata 1073348 for Cortex-A76

Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Add workaround for errata 1220197 for Cortex-A76

Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to t

Add workaround for errata 1220197 for Cortex-A76

Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.

Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Add workaround for errata 1130799 for Cortex-A76

TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address t

Add workaround for errata 1130799 for Cortex-A76

TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.

Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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