1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/interrupt_props.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <plat/common/common_def.h> 15 16 #define PLAT_SOCFPGA_STRATIX10 1 17 #define PLAT_SOCFPGA_AGILEX 2 18 19 #define PLAT_CPUID_RELEASE 0xffe1b000 20 #define PLAT_SEC_ENTRY 0xffe1b008 21 22 /* Define next boot image name and offset */ 23 #define PLAT_NS_IMAGE_OFFSET 0x50000 24 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 25 26 /******************************************************************************* 27 * Platform binary types for linking 28 ******************************************************************************/ 29 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 30 #define PLATFORM_LINKER_ARCH aarch64 31 32 /* SoCFPGA supports up to 124GB RAM */ 33 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 34 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 35 36 37 /******************************************************************************* 38 * Generic platform constants 39 ******************************************************************************/ 40 #define PLAT_PRIMARY_CPU 0 41 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 42 43 /* Size of cacheable stacks */ 44 #define PLATFORM_STACK_SIZE 0x2000 45 46 /* PSCI related constant */ 47 #define PLAT_NUM_POWER_DOMAINS 5 48 #define PLAT_MAX_PWR_LVL 1 49 #define PLAT_MAX_RET_STATE 1 50 #define PLAT_MAX_OFF_STATE 2 51 #define PLATFORM_SYSTEM_COUNT 1 52 #define PLATFORM_CLUSTER_COUNT 1 53 #define PLATFORM_CLUSTER0_CORE_COUNT 4 54 #define PLATFORM_CLUSTER1_CORE_COUNT 0 55 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 56 PLATFORM_CLUSTER0_CORE_COUNT) 57 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 58 59 /* Interrupt related constant */ 60 61 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 62 63 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 64 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 65 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 66 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 67 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 68 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 69 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 70 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 71 72 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 73 #define TSP_SEC_MEM_BASE BL32_BASE 74 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 75 /******************************************************************************* 76 * Platform memory map related constants 77 ******************************************************************************/ 78 #define DRAM_BASE (0x0) 79 #define DRAM_SIZE (0x80000000) 80 81 #define OCRAM_BASE (0xFFE00000) 82 #define OCRAM_SIZE (0x00040000) 83 84 #define MEM64_BASE (0x0100000000) 85 #define MEM64_SIZE (0x1F00000000) 86 87 #define DEVICE1_BASE (0x80000000) 88 #define DEVICE1_SIZE (0x60000000) 89 90 #define DEVICE2_BASE (0xF7000000) 91 #define DEVICE2_SIZE (0x08E00000) 92 93 #define DEVICE3_BASE (0xFFFC0000) 94 #define DEVICE3_SIZE (0x00008000) 95 96 #define DEVICE4_BASE (0x2000000000) 97 #define DEVICE4_SIZE (0x0100000000) 98 99 /******************************************************************************* 100 * BL31 specific defines. 101 ******************************************************************************/ 102 /* 103 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 104 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 105 * little space for growth. 106 */ 107 108 109 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 110 111 #define BL1_RO_BASE (0xffe00000) 112 #define BL1_RO_LIMIT (0xffe0f000) 113 #define BL1_RW_BASE (0xffe10000) 114 #define BL1_RW_LIMIT (0xffe1ffff) 115 #define BL1_RW_SIZE (0x14000) 116 117 #define BL2_BASE (0xffe00000) 118 #define BL2_LIMIT (0xffe1b000) 119 120 #define BL31_BASE (0xffe1c000) 121 #define BL31_LIMIT (0xffe3bfff) 122 123 /******************************************************************************* 124 * Platform specific page table and MMU setup constants 125 ******************************************************************************/ 126 #define MAX_XLAT_TABLES 8 127 #define MAX_MMAP_REGIONS 16 128 129 /******************************************************************************* 130 * Declarations and constants to access the mailboxes safely. Each mailbox is 131 * aligned on the biggest cache line size in the platform. This is known only 132 * to the platform as it might have a combination of integrated and external 133 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 134 * line at any cache level. They could belong to different cpus/clusters & 135 * get written while being protected by different locks causing corruption of 136 * a valid mailbox address. 137 ******************************************************************************/ 138 #define CACHE_WRITEBACK_SHIFT 6 139 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 140 141 #define PLAT_GIC_BASE (0xFFFC0000) 142 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 143 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 144 #define PLAT_GICR_BASE 0 145 146 /******************************************************************************* 147 * UART related constants 148 ******************************************************************************/ 149 #define PLAT_UART0_BASE (0xFFC02000) 150 #define PLAT_UART1_BASE (0xFFC02100) 151 152 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 153 154 #define PLAT_BAUDRATE (115200) 155 #define PLAT_UART_CLOCK (100000000) 156 157 /******************************************************************************* 158 * System counter frequency related constants 159 ******************************************************************************/ 160 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 161 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) 162 163 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 164 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 165 166 /* 167 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 168 * terminology. On a GICv2 system or mode, the lists will be merged and treated 169 * as Group 0 interrupts. 170 */ 171 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 172 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 173 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 174 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 175 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 176 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 177 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 178 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 179 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 180 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 181 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 182 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 183 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 184 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 185 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 186 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 187 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 188 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 189 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 190 191 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 192 193 #define MAX_IO_HANDLES 4 194 #define MAX_IO_DEVICES 4 195 #define MAX_IO_BLOCK_DEVICES 2 196 197 #endif /* PLATFORM_DEF_H */ 198 199