1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/ti/uart/uart_16550.h> 14 #include <lib/xlat_tables/xlat_tables.h> 15 #include <lib/mmio.h> 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 #include "socfpga_private.h" 20 #include "s10_reset_manager.h" 21 #include "s10_memory_controller.h" 22 #include "s10_pinmux.h" 23 #include "s10_clock_manager.h" 24 #include "s10_system_manager.h" 25 26 static entry_point_info_t bl32_image_ep_info; 27 static entry_point_info_t bl33_image_ep_info; 28 29 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 30 { 31 entry_point_info_t *next_image_info; 32 33 next_image_info = (type == NON_SECURE) ? 34 &bl33_image_ep_info : &bl32_image_ep_info; 35 36 /* None of the images on this platform can have 0x0 as the entrypoint */ 37 if (next_image_info->pc) 38 return next_image_info; 39 else 40 return NULL; 41 } 42 43 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 44 u_register_t arg2, u_register_t arg3) 45 { 46 static console_16550_t console; 47 48 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 49 &console); 50 /* 51 * Check params passed from BL31 should not be NULL, 52 */ 53 void *from_bl2 = (void *) arg0; 54 55 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 56 57 assert(params_from_bl2 != NULL); 58 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 59 assert(params_from_bl2->h.version >= VERSION_2); 60 61 /* 62 * Copy BL32 (if populated by BL31) and BL33 entry point information. 63 * They are stored in Secure RAM, in BL31's address space. 64 */ 65 66 bl_params_node_t *bl_params = params_from_bl2->head; 67 68 while (bl_params) { 69 if (bl_params->image_id == BL33_IMAGE_ID) 70 bl33_image_ep_info = *bl_params->ep_info; 71 72 bl_params = bl_params->next_params_info; 73 } 74 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 75 } 76 77 static const interrupt_prop_t s10_interrupt_props[] = { 78 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 79 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 80 }; 81 82 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 83 84 static const gicv2_driver_data_t plat_gicv2_gic_data = { 85 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 86 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 87 .interrupt_props = s10_interrupt_props, 88 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 89 .target_masks = target_mask_array, 90 .target_masks_num = ARRAY_SIZE(target_mask_array), 91 }; 92 93 /******************************************************************************* 94 * Perform any BL3-1 platform setup code 95 ******************************************************************************/ 96 void bl31_platform_setup(void) 97 { 98 /* Initialize the gic cpu and distributor interfaces */ 99 gicv2_driver_init(&plat_gicv2_gic_data); 100 gicv2_distif_init(); 101 gicv2_pcpu_distif_init(); 102 gicv2_cpuif_enable(); 103 } 104 105 const mmap_region_t plat_stratix10_mmap[] = { 106 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 107 MT_MEMORY | MT_RW | MT_NS), 108 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 109 MT_DEVICE | MT_RW | MT_NS), 110 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 111 MT_DEVICE | MT_RW | MT_SECURE), 112 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 113 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 114 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 115 MT_DEVICE | MT_RW | MT_SECURE), 116 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 117 MT_DEVICE | MT_RW | MT_NS), 118 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 119 MT_DEVICE | MT_RW | MT_NS), 120 {0} 121 }; 122 123 /******************************************************************************* 124 * Perform the very early platform specific architectural setup here. At the 125 * moment this is only intializes the mmu in a quick and dirty way. 126 ******************************************************************************/ 127 void bl31_plat_arch_setup(void) 128 { 129 const mmap_region_t bl_regions[] = { 130 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 131 MT_MEMORY | MT_RW | MT_SECURE), 132 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 133 MT_CODE | MT_SECURE), 134 MAP_REGION_FLAT(BL_RO_DATA_BASE, 135 BL_RO_DATA_END - BL_RO_DATA_BASE, 136 MT_RO_DATA | MT_SECURE), 137 #if USE_COHERENT_MEM 138 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 139 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 140 MT_DEVICE | MT_RW | MT_SECURE), 141 #endif 142 {0} 143 }; 144 145 setup_page_tables(bl_regions, plat_stratix10_mmap); 146 enable_mmu_el3(0); 147 } 148 149