1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <drivers/synopsys/dw_mmc.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 18 #include "qspi/cadence_qspi.h" 19 #include "socfpga_handoff.h" 20 #include "socfpga_mailbox.h" 21 #include "socfpga_private.h" 22 #include "s10_clock_manager.h" 23 #include "s10_memory_controller.h" 24 #include "s10_pinmux.h" 25 #include "s10_reset_manager.h" 26 #include "s10_system_manager.h" 27 #include "wdt/watchdog.h" 28 29 30 const mmap_region_t plat_stratix10_mmap[] = { 31 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 32 MT_MEMORY | MT_RW | MT_NS), 33 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 34 MT_DEVICE | MT_RW | MT_NS), 35 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 36 MT_DEVICE | MT_RW | MT_SECURE), 37 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 38 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 39 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 42 MT_DEVICE | MT_RW | MT_NS), 43 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 44 MT_DEVICE | MT_RW | MT_NS), 45 {0}, 46 }; 47 48 boot_source_type boot_source; 49 50 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 51 u_register_t x2, u_register_t x4) 52 { 53 static console_16550_t console; 54 handoff reverse_handoff_ptr; 55 56 generic_delay_timer_init(); 57 58 if (socfpga_get_handoff(&reverse_handoff_ptr)) 59 return; 60 config_pinmux(&reverse_handoff_ptr); 61 boot_source = reverse_handoff_ptr.boot_source; 62 63 config_clkmgr_handoff(&reverse_handoff_ptr); 64 enable_nonsecure_access(); 65 deassert_peripheral_reset(); 66 config_hps_hs_before_warm_reset(); 67 68 watchdog_init(get_wdt_clk()); 69 70 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 71 &console); 72 73 socfpga_delay_timer_init(); 74 init_hard_memory_controller(); 75 } 76 77 78 void bl2_el3_plat_arch_setup(void) 79 { 80 81 struct mmc_device_info info; 82 const mmap_region_t bl_regions[] = { 83 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 84 MT_MEMORY | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 86 MT_CODE | MT_SECURE), 87 MAP_REGION_FLAT(BL_RO_DATA_BASE, 88 BL_RO_DATA_END - BL_RO_DATA_BASE, 89 MT_RO_DATA | MT_SECURE), 90 #if USE_COHERENT_MEM_BAR 91 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 92 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 93 MT_DEVICE | MT_RW | MT_SECURE), 94 #endif 95 {0}, 96 }; 97 98 setup_page_tables(bl_regions, plat_stratix10_mmap); 99 100 enable_mmu_el3(0); 101 102 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 103 104 info.mmc_dev_type = MMC_IS_SD; 105 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 106 107 switch (boot_source) { 108 case BOOT_SOURCE_SDMMC: 109 dw_mmc_init(¶ms, &info); 110 socfpga_io_setup(boot_source); 111 break; 112 113 case BOOT_SOURCE_QSPI: 114 mailbox_set_qspi_open(); 115 mailbox_set_qspi_direct(); 116 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 117 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 118 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 119 socfpga_io_setup(boot_source); 120 break; 121 122 default: 123 ERROR("Unsupported boot source\n"); 124 panic(); 125 break; 126 } 127 } 128 129 uint32_t get_spsr_for_bl33_entry(void) 130 { 131 unsigned long el_status; 132 unsigned int mode; 133 uint32_t spsr; 134 135 /* Figure out what mode we enter the non-secure world in */ 136 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 137 el_status &= ID_AA64PFR0_ELX_MASK; 138 139 mode = (el_status) ? MODE_EL2 : MODE_EL1; 140 141 /* 142 * TODO: Consider the possibility of specifying the SPSR in 143 * the FIP ToC and allowing the platform to have a say as 144 * well. 145 */ 146 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 147 return spsr; 148 } 149 150 151 int bl2_plat_handle_post_image_load(unsigned int image_id) 152 { 153 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 154 155 switch (image_id) { 156 case BL33_IMAGE_ID: 157 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 158 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 159 break; 160 default: 161 break; 162 } 163 164 return 0; 165 } 166 167 /******************************************************************************* 168 * Perform any BL3-1 platform setup code 169 ******************************************************************************/ 170 void bl2_platform_setup(void) 171 { 172 } 173 174